MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 213

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

DDRQA — Port QA Data Direction Register
QACR0 — QADC64 Control Register 0
5.12.4 Port Data Direction Register
RESET:
5.12.5 QADC64 Control Register 0 (QACR0)
RESET:
MC68F375
REFERENCE MANUAL
Bit(s)
DDQ
Bit(s)
MUX
MSB
MSB
15:8
15:8
15
A7
15
7:0
7:0
0
0
Control register 0 establishes the QCLK with prescaler parameter fields and defines
whether external multiplexing is enabled. All of the implemented control register fields
can be read or written, reserved fields read zero and writes have no effect. They are
typically written once when the software initializes the QADC64, and not changed
afterwards.
DDQA
RESERVED
DDQA[7:0]
14
14
PQA[0:7]
PQB[0:7]
6
0
0
Name
Name
—
DDQA
13
13
5
0
0
Port A pins are referred to as PQA when used as an 8-bit input/output port. Port A can also be
used for analog inputs (AN[59:52]), and external multiplexer address outputs (MA[2:0]).
Port B pins are referred to as PQB when used as an 8-bit input only port. Port B can also be used
for non-multiplexed (AN[51:48])/AN[3:0]) and multiplexed (ANz, ANy, ANx, ANw) analog inputs.
Bits in this register control the direction of the port QA pin drivers when pins are configured for I/
O. Setting a bit configures the corresponding pin as an output; clearing a bit configures the cor-
responding pin as an input. This register can be read or written at any time.
Reserved
DDQA
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
TRG
12
12
4
0
0
Table 5-9 PORTQA, PORTQB Bit Settings
Freescale Semiconductor, Inc.
DDQA
11
11
3
0
0
For More Information On This Product,
RESERVED
Table 5-10 DDRQA Bit Settings
DDQA
10
10
2
0
0
Go to: www.freescale.com
DDQA
9
1
0
9
0
Rev. 25 June 03
DDQA
8
0
0
8
0
7
0
7
1
Description
Description
PSH
6
0
6
0
5
0
5
1
RESERVED
4
0
4
1
PSA
3
0
3
0
2
0
2
1
0xYF F40A
0xYF F408
MOTOROLA
PSL
1
0
1
1
5-37
LSB
LSB
0
0
0
1