MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 370

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

9.6 Multiple Input Signature Calculator (MISC)
MC68F375
REFERENCE MANUAL
stored in the array, the user places one or both of the TPU3 units in emulation mode.
The RAM array is then controlled by the TPU3 units and disconnected from the IMB3.
To use the DPTRAM for microcode accesses, set the EMU bit in the corresponding
TPU3 module configuration register. Through the auxiliary buses, the TPU3 units can
access word instructions simultaneously at a rate of up to 40 MHz.
When the RAM array is being used by either or both of the TPU3 units, all accesses
via the IMB3 are disabled. The control registers have no effect on the RAM array.
Accesses to the array are ignored, allowing an external RAM to replace the function of
the general-purpose RAM array.
The contents of the RAM are validated using a multiple input signature calculator
(MISC). MISC reads of the RAM are performed only when the MC68F375 is in emula-
tion mode and the MISC is enabled (MISEN = 1 in the DPTMCR).
Refer to
ation in emulation mode.
The integrity of the RAM data is ensured through the use of a MISC. The RAM data is
read in reverse address order and a unique 32-bit signature is generated based on the
output of these reads. MISC reads are performed when one of the TPU3 modules
does not request back-to-back accesses to the RAM provided that the MISEN bit in
the MC68F375 MCR is set.
The MISC generates the DPTRAM signature based on the following polynomial:
After the entire RAM has been read and a signature has been calculated, the MISC
sets the MISF bit in the MC68F375 MCR. The host should poll this bit and enter a han-
dling routine when the bit is found to be set.
The signature should be then read from the MISRH and MISRL registers and the host
determines if it matches the predetermined signature.
The MISRH and MISRL registers are updated each time the MISC completes reading
the entire RAM regardless of whether or not the previous signature has been read or
not. This ensures that the host reads the most recently generated signature.
The MISC can be disabled by clearing the MISEN bit in the MC68F375 MCR. Note that
the reset state of the MC68F375 MISEN is disabled.
8.3.6 Emulation Support
Freescale Semiconductor, Inc.
For More Information On This Product,
DUAL-PORT TPU RAM (DPTRAM)
G x
Go to: www.freescale.com
Rev. 25 June 03
=
for more information in TPU3 and DPTRAM oper-
1
+ +
x
x
2
+
x
22
+
x
31
MOTOROLA
9-8