MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 67

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
MOVE to SR
MULS/MULU
MOVE USP
ORI to CCR
Instruction
MOVE from
ORI to SR
MOVEC
MOVES
MOVEM
RESET
MOVEP
MOVEQ
NBCD
NEGX
ROXR
ROXL
NEG
NOP
NOT
ROR
PEA
ROL
RTD
SR
ORI
OR
1
1
1
1
1
1
1
Dn, (d16, An)
(d16, An), Dn
<ea>, Dh : Dl
#<data>, SR
#<data>, Dn
#<data>, Dn
#<data>, Dn
#<data>, Dn
#<data>, Dn
SR, <ea>
<ea>, SR
Operand
list, <ea>
<ea>, list
Rn, <ea>
<ea>, Rn
<ea>, Dn
<ea>, Dn
Dn, <ea>
#<data>,
#<data>,
USP, An
An, USP
<ea>, Dl
Syntax
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Rc, Rn
Rn, Rc
<ea>
<ea>
<ea>
<ea>
<ea>
<ea>
<ea>
<ea>
<ea>
<ea>
none
CCR
none
#d
Table 3-2 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
16
32
32
16, 32
Operand
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8
16, 32
16, 32
none
none
Size
16
32
32
16
16
32
32
32
32
16
16
32
16
16
16
16
16
8
8
CENTRAL PROCESSOR UNIT
32
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32
32
32
64
SR
Source
USP
An
Rc
Rn
Listed registers
Source
Dn [31 : 24]
Dn [15 : 8]
(An
(An
Immediate data
Rn
Source using SFC
Source Destination
(signed or unsigned)
0
0
0
PC
Destination
Source
Data
Source
Source ; SR
SP
Assert RESET line
(SP)
Rev. 25 June 03
Destination
Destination
Destination
4
2
d)
d
USP
Rn
Rc
Destination using DFC
Destination
Destination
PC; SP
An
Destination
CCR
4)
SP; <ea>
PC
SR
Listed registers
Dn [31 : 24]; (An
C
(An
Destination
10
(An
Dn [15 : 8]; (An
SR
X
X
4
SR
Destination
Destination
C
Destination
X
d
d); Dn [23 : 16]
Rn
d
Destination
Destination
SP
4); Dn [7 : 0]
Destination
Destination
Destination
SP
Description
d
d
2)
6)
(An
(An
Dn [23 : 16];
Dn [7 : 0]
d
d
C
2);
6)
X
C
MOTOROLA
3-13