MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 465

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.6.1 Output Flip-Flop and Pin
MC68F375
REFERENCE MANUAL
range from 7.8 milliseconds to 2.0 seconds (assuming a 16.78 MHz MCU clock). By
reducing the counting value, the output signal period can be reduced. The period can
be as fast as 488 microseconds (2.048 KHz) with 12 bits of resolution, as fast as 30.5
microseconds (32.768 KHz) with 8 bits of resolution, and as fast as 7.6 microseconds
(131.072 KHz) with 6 bits of resolution (still assuming a 16.78 MHz system clock and
a first stage prescaler divide-by-2 clock selection). A block diagram of the PWMSM is
shown in
The output flip-flop is the basic output mechanism of the PWMSM. Except when the
required pulse width is 0% or 100%, the output flip-flop is set at the beginning of each
period and is cleared at the end of the designated pulse width. The polarity of the out-
put pulse can be selected in software. The output of the PWMSM is connected to an
external, output-only pin. When the PWMSM is not required, and is disabled by clear-
ing the EN bit in the PWMSIC register, this pin serves as a digital output-only port pin.
When the PWMSM is disabled, the POL bit in the SIC register serves as an output port
bit.
Figure 13-13 Pulse Width Modulation Submodule Block Diagram
CLK2
Figure
PCLK1
CLK1 CLK0
13-13.
Next period register
PWMA
16-bit comparator
16-bit up counter
/ 256 prescaler
Period register
Freescale Semiconductor, Inc.
(N
PWMA2
PWMA1
PWMC
For More Information On This Product,
Clock
select
CONFIGURABLE TIMER MODULE (CTM9)
count
)
Go to: www.freescale.com
Enable
Match
Rev. 25 June 03
FLAG
sequencer
Control register bits
Interrupt
Submodule bus
control
LOAD
State
IL2
IL1
IL1
Load
IL0 IARB3
Set
Clear
Pulse width register
PWMB
16-bit comparator
Next pulse width
register PWMB1
flip-flop
Output
PWMB2
EN
Clear
Match
Output
buffer
POL
detect
Zero
All zeros
PIN
Output
pin
MOTOROLA
13-39