MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 251

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
13:10
7:0
15
14
9
8
WOMQ
MSTR
CPHA
SPBR
Name
CPOL
BITS
Master/slave mode select
0 = QSPI is a slave device and only responds to externally generated serial transfers.
1 = QSPI is the system master and can initiate transmission to external SPI devices.
Wired-OR mode for QSPI pins. This bit controls the QSPI pins regardless of whether they are
used as general-purpose outputs or as QSPI outputs, and regardless of whether the QSPI is
enabled or disabled.
0 = Pins designated for output by DDRQS operate in normal mode.
1 = Pins designated for output by DDRQS operate in open drain mode.
Bits per transfer. In master mode, when BITSE is set in a command RAM byte, BITS determines
the number of data bits transferred. When BITSE is cleared, eight bits are transferred regardless
of the value in BITS. In slave mode, the BITS field always determines the number of bits the QSPI
will receive during each transfer before storing the received data.
Data transfers from 8 to 16 bits are supported. Illegal (reserved) values default to eight
6-14
Clock polarity. CPOL is used to determine the inactive state of the serial clock (SCK). It is used
with CPHA to produce a desired clock/data relationship between master and slave devices.
0 = The inactive state of SCK is logic zero.
1 = The inactive state of SCK is logic one.
Clock phase. CPHA determines which edge of SCK causes data to change and which edge
causes data to be captured. CPHA is used with CPOL to produce a desired clock/data relation-
ship between master and slave devices.
0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK.
1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
Serial clock baud rate. The QSPI uses a modulus counter to derive the SCK baud rate from the
MCU system clock. Baud rate is selected by writing a value from 2 to 255 into SPBR. The follow-
ing equation determines the SCK baud rate:
Refer to
shows the number of bits per transfer.
Freescale Semiconductor, Inc.
6.7.5.2 Baud Rate Selection
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Table 6-13 SPCR0 Bit Settings
Table 6-14 Bits Per Transfer
0001 to 0111
BITS[3:0]
0000
1000
1001
1010
1011
1100
1101
1110
1111
Go to: www.freescale.com
Rev. 25 June 03
Reserved (defaults to 8)
SCK Baud Rate
Bits per Transfer
for more information.
Description
16
10
11
12
13
14
15
8
9
=
-------------------------- -
2 SPBR
f
SYS
MOTOROLA
bits.Table
6-17