MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 211

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

QADC64MCR — QADC64 Module Configuration Register
5.12.1 QADC64 Module Configuration Register
RESET:
5.12.2 QADC64 Interrupt Register
MC68F375
REFERENCE MANUAL
STOP
Bit(s)
MSB
13:8
15
6:4
3:0
15
14
0
7
All QADC64 analog channel/port pins that are not used for analog input channels can
be used as digital port pins. Port values are read/written by accessing the port A and
B data registers (PORTQA and PORTQB). Port A pins are specified as inputs or out-
puts by programming the port data direction register (DDRQA). Port B is an input only
port.
QADC64INT specifies the priority level of QADC64 interrupt requests and the vector
provided. The interrupt level for queue 1 and queue 2 may be different. The interrupt
register is read/write accessible in supervisor data space only. The implemented inter-
rupt register fields can be read and written, reserved bits read zero and writes have
no effect. They are typically written once when the software initializes the QADC, and
not changed afterwards.
FRZ
14
0
Name
STOP
SUPV
IARB
FRZ
—
—
13
0
Low-power stop mode enable. When the STOP bit is set, the clock signal to the QADC64 is dis-
abled, effectively turning off the analog circuitry.
0 = Enable QADC64 clock.
1 = Disable QADC64 clock.
assertion of the IMB3 FREEZE signal.
0 = QADC64 ignores the IMB3 FREEZE signal.
1 = QADC64 finishes any current conversion, then freezes.
Reserved
sor or unrestricted.
0 = Only the module configuration register, test register, and interrupt register are designated as
1 = All QADC64 registers and tables are designated as supervisor-only data space.
Reserved
Interrupt arbitration number. IARB determines QADC64 interrupt arbitration priority. An IARB
field can be assigned a value from 0b0001 (lowest priority) to 0b1111 (highest value). Note that
the logic associated with the IARB field is implemented for bus masters with interrupt acknowl-
edge cycles (IACK).
FREEZE assertion response. The FRZ bit determines whether or not the QADC64 responds to
Supervisor/unrestricted data space. The SUPV bit designates the assignable space as supervi-
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
12
0
supervisor-only data space. Access to all other locations is unrestricted.
Freescale Semiconductor, Inc.
RESERVED
11
Table 5-7 QADC64MCR Bit Settings
0
For More Information On This Product,
10
0
Go to: www.freescale.com
9
0
Rev. 25 June 03
8
0
SUPV
7
1
Description
6
0
RESERVED
5
0
4
0
3
0
2
0
0xYF F400
IARB
MOTOROLA
1
0
5-35
LSB
0
0