MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 228

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

5.13 Analog Multiplexer Submodule
5.13.1 Signal Descriptions
5.13.1.1 External Pins (Connected to Pads)
5.13.1.2 Internal Pins (Connected to QADC64)
MC68F375
REFERENCE MANUAL
The conversion result is unsigned, left justified data. Unused bits return zero when
read.
The analog multiplexer (AMUX) submodule expands the channel capacity of the
QADC64 analog-to-digital converter inputs to a maximum of 27 analog channels
(using only the on-chip multiplexer, 41 with the addition of off-chip multiplexers). The
AMUX does not have an inter-module bus (IMB3) interface; control is through the
QADC64.
The AMUX is a “high voltage” device requiring 5 V nominal. There is no on-board
charge pump as with the previous UDR implementation of the AMUX. Performance of
the AMUX should be superior to that of an external multiplexer because of the greatly
reduced parasitic capacitances. In addition, precautions have been taken to insure
that the input current requirement is as low as possible.
The architecture and pin naming of the AMUX were modeled after the QADC64 oper-
ating in external multiplexer mode. Use of this feature of the QADC64 is described in
5.7 External Multiplexing
AMUX is used with the QADC64, it replaces the external multiplexers. The software
model is identical and the system performance is improved.
ANX0–ANX15, analog input pins, extended. These 16 analog input channels are
divided into 2 groups of 8 inputs: ANX0–14 even, ANX1–15 odd. Each group is con-
nected to a separate multiplexer within the AMUX. These pads are unique to the
AMUX.
V
V
See table
AMMA[2:0]. Multiplexer address inputs. These pins are decoded into 8 select lines
that steer the 4 multiplexers within the AMUX in parallel. The final stage selection
between the 4 multiplexers is done within the QADC64. On the MC68F375 only 2 ana-
log multiplexers are selected.
Assuming that these lines change simultaneously, break-before-make switching
ensures that on each channel change, all multiplexer outputs are opened before the
new one is selected. This prevents 2 inputs in the same mux from being connected to
the mux output at any one time.
DDA
DD
, V
, V
SS
SSA
, digital power, is shared by the QADC64 and the AMUX.
Table 5-22
, analog power, is shared by the QADC64 and the AMUX.
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Freescale Semiconductor, Inc.
for a summary of this section.
For More Information On This Product,
Operation, and is illustrated in
Go to: www.freescale.com
Rev. 25 June 03
Figure
5-13. When the
MOTOROLA
5-52