MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 366

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

9.4.2 DPTRAM Test Register
DPTTCR — Test Register 0x30 0002
9.4.3 Ram Base Address Register (DPTBAR)
MC68F375
REFERENCE MANUAL
Bit(s)
14:11
7:0
15
10
9
8
DPTTCR is used only during factory testing of the MCU.
The DPTBAR register is used to specify the 16 MSBs of the starting DPT RAM array
location in the memory map.
This register can be written only once after a reset and must be written after the
DPRTAM is enabled (DPTMCR STOP = 0b0). This prevents runaway software from
inadvertently re-mapping the array. Since the locking mechanism is triggered by the
first write after reset, the base address of the array should be written in a single oper-
ation. Writing only one half of the register will prevent the other half from being written.
MISEN
Name
STOP
RASP
MISF
—
—
Low power stop (sleep) mode
0 = DPTRAM clocks running
1 = DPTRAM clocks shut down
Only the STOP bit in the DPTMCR may be accessed while the STOP bit is asserted. Accesses
to other DPTRAM registers may result in unpredictable behavior. Note also that the STOP bit
should be set and cleared independently of the other control bits in this register to guarantee
proper operation. Changing the state of other bits while changing the state of the STOP bit may
result in unpredictable behavior.
Refer to
Reserved
Multiple input signature flag. MISF is readable at any time. This flag bit should be polled by the
host to determine if the MISC has completed reading the RAM. If MISF is set, the host should
read the MISRH and MISRL registers to obtain the RAM signature.
0 = First signature not ready
1 = MISC has read entire RAM. Signature is latched in MISRH and MISRL and is ready to be
Multiple input signature enable. MISEN is readable and writable at any time. The MISC will only
operate when this bit is set and the MC68F375 is in TPU3 emulation mode. When enabled, the
MISC will continuously cycle through the RAM addresses, reading each and adding the contents
to the MISR. In order to save power, the MISC can be disabled by clearing the MISEN bit.
0 = MISC disabled
1 = MISC enabled
Ram area supervisor/user program/data. The RAM array may be placed in supervisor or unre-
stricted Space. When placed in supervisor space, (RASP = 1), only a supervisor may access the
array. If a supervisor program is accessing the array, normal read/write operation will occur. If a
user program is attempting to access the array, the access will be ignored and the address may
be decoded externally.
0 = Both supervisor and user access to RAM allowed
1 = Supervisor access only to RAM allowed
Reserved
read.
Freescale Semiconductor, Inc.
9.5.4 Stop Operation
For More Information On This Product,
Table 9-2 DPTMCR Bit Settings
DUAL-PORT TPU RAM (DPTRAM)
Go to: www.freescale.com
Rev. 25 June 03
for more information.
Description
MOTOROLA
9-4