MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 447

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
14:12
15
11
10
9
8
7
6
5
FORCE
IARB3
Name
IL[2:0]
FLAG
BSL
IEN
—
IN
—
Event flag. The FLAG bit is set whenever an input capture or output compare event occurs. This
flag bit is set only by the hardware and cleared only by the software or by a system reset. If the
IL field is non-zero, and the IEN bit is set, an interrupt request is generated when the FLAG bit
is set.
In IC mode, if a subsequent input capture event occurs while the FLAG bit is set, the new value
is latched and the FLAG bit remains set. In OC mode, if a subsequent output compare event
occurs while the FLAG bit is set, the compare occurs normally and the FLAG bit remains set. In
OCT mode, if a subsequent output compare event occurs while the FLAG bit is set, the toggle
of the output signal occurs as normal and the FLAG bit remains set. In OP mode, if a subsequent
internal compare event occurs while the FLAG bit is set, the compare occurs normally and the
FLAG bit remains set.
To clear the flag, the software must first read the bit (as ‘1’) then write a ‘0’ to the bit. The flag
clearing mechanism will work only if no flag setting event occurs between the read and write
operations; if a FLAG setting event occurs between the read and write operations, the FLAG bit
will not be cleared.
0 = An input capture or output compare event has not occurred.
1 = An input capture or output compare event has occurred.
Interrupt level. The three interrupt level bits are read/write control bits that select the priority level
of interrupt requests made by the SASM. These bits can be read or written at any time and are
cleared by reset. These bits affect both SASM channels, not just channel A.
000 = Interrupt disabled.
001 = Interrupt level 1 (lowest).
010 = Interrupt level 2.
011 = Interrupt level 3.
100 = Interrupt level 4.
101 = Interrupt level 5.
110 = Interrupt level 6.
111 = Interrupt level 7 (highest).
Interrupt arbitration bit 3. The read/write IARB3 bit works in conjunction with the IARB[2:0] field
in the BIUSM module configuration register. Each module that generates interrupt requests on
the IMB must have a unique value in the arbitration field (IARB). This interrupt arbitration iden-
tification number is used to arbitrate for the IMB when modules generate simultaneous interrupts
of the same priority. This bit affects both SASM channels, not just channel A.
Interrupt enable. This control bit enables interrupts on channel A when the FLAG bit is set and
the IL[2:0] field is non-zero. This bit is cleared by reset
0 = Interrupts disabled.
1 = Interrupts enabled.
Reserved
Time base bus select. This control bit selects the time base bus to be connected to SASM chan-
nel A. This bit is cleared by reset.
0 = Time base bus A selected.
1 = Time base bus B selected.
Input pin status. In input mode (IC), the IN bit reflects the logic state present on the correspond-
ing input pin (after being Schmitt triggered and synchronized). In the output modes (OC, OCT
and OP), the IN bit value reflects the state of the output of the output flip-flop. The IN bit is a read-
only bit; writing to it has no effect. Reset has no effect on this bit.
Reserved
Supervisor/user data space. The SUPV bit places the SCIM2E global registers in either super-
visor or user data space. The FLAG bit is not affected by the use of the FORCE bit.
0 = No action
1 = Force output flip-flop to behave as if an output compare has just occurred.
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Table 13-7 SICA Bit Settings
Go to: www.freescale.com
Rev. 25 June 03
Description
MOTOROLA
13-21