MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 152

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.8 Interrupts
4.8.1 Interrupt Exception Processing
4.8.2 Interrupt Priority and Recognition
MC68F375
REFERENCE MANUAL
Interrupt recognition and servicing involve complex interaction between the SCIM2E,
the CPU32, and a device or module requesting interrupt service. This discussion pro-
vides an overview of the entire interrupt process. Chip-select logic can also be used to
respond to interrupt requests. Refer to
The CPU32 handles interrupts as a type of asynchronous exception. An exception is
an event that preempts normal processing. Exception processing makes the transition
from normal instruction execution to execution of a routine that deals with an excep-
tion. Each exception has an assigned vector that points to an associated handler
routine. These vectors are stored in a vector table located from 0x00000 to 0x001FF.
The CPU32 uses vector numbers to calculate displacement into the table. Refer to
Exception Processing
The CPU32 provides seven levels of interrupt priority (1–7), seven automatic interrupt
vectors, and 200 assignable interrupt vectors. All interrupts with priorities less than
seven can be masked by the interrupt priority (IP) field in the condition code register
(CCR).
The IP field consists of CCR bits [7:5]. Binary values 0b000 to 0b111 provide eight pri-
ority masks. Each mask prevents an interrupt request of a priority less than or equal
to the mask value (except for IRQ7) from being recognized. When the IP field contains
0b000, no interrupt is masked. During exception processing, the IP field is set to the
priority of the interrupt being serviced.
There are seven interrupt request signals (IRQ[7:1]) with corresponding external pins
that can be asserted by microcontroller modules or external devices. Simultaneous
requests of different priorities can be made. Internal assertion of an interrupt request
line does not affect the state of the corresponding MCU pin.
External interrupt requests are routed to the CPU32 via the EBI and SCIM2E interrupt
control logic. All requests for interrupt service are treated as if they come from internal
modules. The CPU32 treats external interrupt requests as if they come from the
SCIM2E.
The IRQ[6:1] pins are active-low level-sensitive inputs. The IRQ7 pin is an active-low
transition-sensitive input; it requires both an edge and a voltage level to be valid.
When TSC assertion takes effect, internal signals are forced to val-
ues that can cause inadvertent mode selection. Once the output
drivers change state, the MCU must be powered down and restarted
before normal operation can resume.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
for more information.
Go to: www.freescale.com
Rev. 25 June 03
4.9 Chip Selects
NOTE
for more information.
MOTOROLA
4-70
3.9