MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 150

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.7.8.5 Breakpoint Mode Selection
MC68F375
REFERENCE MANUAL
NOTES:
Select Pin
DATA10
1. Because DATA[7:0] are unavailable in 8-bit expanded mode, these pins default to the reset configurations noted.
2. The FASTREF function is used only at reset and serves no purpose during normal operation.
3. The CSE and CSM emulation chip selects do not function in 8-bit expanded mode.
Just as in 16-bit expanded mode, DATA[15:12] allow implementation dependent dis-
abling of on-chip ROM and/or flash EEPROM modules. Refer to
which modules on the MC68F375 are affected by these pins.
Background debug mode (BDM) is enabled when the breakpoint (BKPT) pin is sam-
pled at logic zero at the release of RESET. Subsequent assertion of the BKPT pin or
the internal breakpoint signal (for instance, execution of the CPU32 BGND instruction)
will place the CPU32 in BDM.
If BKPT is sampled at logic one at the rising edge of RESET, BDM is disabled. Asser-
tion of the BKPT pin or execution of the BKPT instruction will result in normal
breakpoint exception processing. Execution of the BGND instruction will cause an ille-
gal instruction exception to be taken.
BDM remains enabled until the next system reset. BKPT is relatched and synchro-
nized on each rising transition of RESET and must be held low for at least two clock
cycles prior to RESET negation for BDM to be enabled. BKPT assertion logic must be
designed with special care. If BKPT assertion extends into the first bus cycle following
the release of RESET, the bus cycle could inadvertently be tagged with a breakpoint.
DATA8
DATA9
NA
NA
NA
1
1
1
Table 4-30 Partially (8-bit) Expanded Mode Reset Configuration
ADDR[22:19]/CS[9:6]/PC[6:3]
ADDR23/CS10/ECLK
Pin(s) or Module(s)
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
IRQ[7:1]/PF[7:1]
Freescale Semiconductor, Inc.
FASTREF/PF0
FC0/CS3/PC0
FC2/CS5/PC2
BGACK/CSE
DSACK0/PE0
DSACK1/PE1
AVEC/PE2
RMC/PE3
SIZ0/PE6
SIZ1/PE7
BG/CSM
CSBOOT
For More Information On This Product,
Affected
FC1/PC1
BR/CS0
DS/PE4
AS/PE5
3
Go to: www.freescale.com
3
Rev. 25 June 03
Default Function
(Pin Held High)
FASTREF
DSACK0
DSACK1
IRQ[7:1]
AVEC
RMC
SIZ0
SIZ1
DS
AS
2
8-bit CSBOOT
CS[10:6]
BGACK
CS0
CS3
FC1
CS5
BG
Table 4-29
Alternate Function
(Pin Held Low)
PF[7:1]
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PF0
MOTOROLA
above for
4-68