MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 339

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

IMASK — Interrupt Mask Register
IFLAG — Interrupt Flag Register
7.8.12 Interrupt Mask Register
7.8.13 Interrupt Flag Register
MC68F375
REFERENCE MANUAL
MSB
MSB
15
15
Bit(s)
Bit(s)
15:8,
15:8,
0
0
RESET:
RESET:
7:0
7:0
14
14
0
0
IMASKH,
IFLAGH,
IMASKL
IFLAGL
Name
Name
13
13
0
0
12
12
0
0
IMASKH
IFLAGH
IMASK contains two 8-bit fields, IMASKH and IMASKL. IMASK can be accessed with a 16-
bit read or write, and IMASKH and IMASKL can be accessed with byte reads or writes.
IMASK contains one interrupt mask bit per buffer. It allows the CPU to designate which buff-
ers will generate interrupts after successful transmission/reception. Setting a bit in IMASK
enables interrupt requests for the corresponding message buffer.
IFLAG contains two 8-bit fields, IFLAGH and IFLAGL. IFLAG can be accessed with a 16-bit
read or write, and IFLAGH and IFLAGL can be accessed with byte reads or writes.
IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception sets
the corresponding IFLAG bit and, if the corresponding IMASK bit is set, an interrupt request
will be generated.
To clear an interrupt flag, first read the flag as a one, and then write it as a zero. Should a
new flag setting event occur between the time that the CPU reads the flag as a one and
writes the flag as a zero, the flag is not cleared. This register can be written to zeros only.
Table 7-23 Fault Confinement State Encoding
Freescale Semiconductor, Inc.
11
11
0
0
For More Information On This Product,
Table 7-24 IMASK Bit Settings
Table 7-25 IFLAG Bit Settings
FCS[1:0]
CAN 2.0B CONTROLLER MODULE
10
10
0
0
1X
00
01
Go to: www.freescale.com
9
0
9
0
Rev. 25 June 03
8
0
8
0
7
0
7
0
Error passive
Error active
Bus State
Description
Description
Bus off
6
0
6
0
5
0
5
0
4
0
4
0
IMASKL
IFLAGL
3
0
3
0
2
0
2
0
0xYF F0A2
0xYF F0A4
MOTOROLA
1
0
1
0
LSB
LSB
7-33
0
0
0
0