MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 559

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

D.17.2 Host CPU Initialization of the SIOP Function
D.17.3 SIOP Function Performance
MC68F375
REFERENCE MANUAL
in input only mode, the data shifted out is ignored. In clock-only mode SIOP_DATA is
still shifted. Note that no ‘justifying’ of SIOP_DATA is performed by the TPU, (e.g., if
an 8-bit bi-directional transfer is made, shifting lsb first, then the bottom byte of
SIOP_DATA will be shifted out and the input data will be shifted into the upper byte of
SIOP_DATA).
The CPU initializes the SIOP function by:
The TPU then starts the data transfer, and issues an interrupt request when the trans-
fer is complete.
Once the function has been initialized, the CPU only needs to write SIOP_DATA with
the new data and issue a HSR %11 to initiate a new transfer. In input or clock-only
modes, just the HSR %11 is required.
Like all TPU functions, the performance limit of the SIOP function in a given application
is dependent to some extent on the service time (latency) associated with other active
TPU channels. This is due to the operational nature of the scheduler. Where two
channels are being used for a uni-directional system, and no other TPU channels are
active, the maximum baud rate is approximately 230 KHz at a bus speed of 16.77
MHz. A three-channel bi-directional system under the same conditions has a maxi-
mum baud rate of approximately 200 KHz. When more TPU channels are active,
these performance figures will be degraded, however, the scheduler assures that the
worst case latency in any TPU application can be closely approximated. It is recom-
mended that the guidelines given in the TPU reference manual be used along with the
information given in the SIOP state timing table to perform an analysis on any pro-
posed TPU application that appears to approach the performance limits of the TPU.
1. Disabling the channel by clearing the two channel priority bits
2. Selecting the SIOP function on the channel by writing the assigned SIOP func-
3. Writing CHAN_CONTROL in the clock channel parameter RAM
4. Writing HALF_PERIOD, BIT_D and XFER_SIZE in the clock channel parame-
5. Writing SIOP_DATA if the data output is to be used
6. Selecting the required operating mode via the two host sequence bits
7. Issuing a host service request type %11
8. Enabling service by assigning H, M or L priority to the clock channel via the two
tion number to the function select bits
ter RAM to determine the speed, shift direction and size of the transfer
channel priority bits
SIOP_DATA is not buffered. The CPU should only access it between
completion of one transfer and the start of the next.
Freescale Semiconductor, Inc.
For More Information On This Product,
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TPU ROM FUNCTIONS
Rev. 25 June 03
NOTE
MOTOROLA
D-45