MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 472

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
14:12
10:8
15
11
7
6
5
IARB3
Name
IL[2:0]
LOAD
FLAG
PIN
—
—
Period completion status. The FLAG bit is a status bit that indicates when the PWM output
period has been completed. The FLAG bit is set by the hardware each time a PWM period is
completed. Whenever the PWM is enabled, the FLAG bit is set immediately to indicate that the
contents of the buffer registers PWMA2 and PWMB2 have been updated, and that the period
using these new values has started. It also indicates that the user accessible period and pulse
width registers PWMA1 and PWMB1 can be loaded with values for the next PWM period. Once
set, the FLAG bit will remain set and will not be affected by any subsequent period completions,
until it is cleared by the software.
The FLAG bit can only be cleared by software. To clear the flag, the software must first read the
bit (as ‘one’) then write a ‘zero’ to the bit. Writing a one to the FLAG bit has no effect. When the
PWM is disabled the FLAG bit remains in the cleared state. The flag clearing mechanism will
work only if no flag setting event occurs between the read and write operations; if a FLAG setting
event occurs between the read and write operations, the FLAG bit will not be cleared.
When the interrupt level set by the interrupt level bit IL[2:0] is not equal to zero, an interrupt
request is generated when the FLAG bit is set. Before returning from the interrupt service rou-
tine, the FLAG bit should be cleared by software to prevent the PWMSM from immediately
generating another interrupt request on the IMB.
0 = PWM period not completed.
1 = PWM period completed.
Interrupt level. The three interrupt level bits select the interrupt level of requests made by the
PWMSMt.
000 = Interrupt disabled
001 = Interrupt level 1 (lowest)
010 = Interrupt level 2
011 = Interrupt level 3
100 = Interrupt level 4
101 = Interrupt level 5
110 = Interrupt level 6
111 = Interrupt level 7 (highest)
Interrupt arbitration. The read/write IARB3 bit works in conjunction with the IARB[2:0] field in the
BIUSM module configuration register. Each module that generates interrupt requests on the IMB
must have a unique value in the arbitration field (IARB). This interrupt arbitration identification
number is used to arbitrate for the IMB when modules generate simultaneous interrupts of the
same priority. The IARB3 bit is cleared by reset.
Reserved
Output pin status. The PIN bit is a status bit that indicates the logic state present on the output
pin. The software can thus monitor the waveform being created on the output pin. PIN is a read-
only bit; writing to it has no effect.
0 = Logic zero state present on the output pin.
1 = Logic one state present on the output pin.
Reserved
Load control. The LOAD bit is a control bit that allows the software to reinitialize the PWMSM
and start a new PWM period without causing a glitch on the PWM output signal.
0 = No action.
1 = Load period and pulse width registers.
This bit is always read as a zero. Writing a one to this bit results in the following immediate
actions:
– The contents of PWMA1 (period value) are transferred to PWMA2,
– The contents of PWMB1 (pulse width value) are transferred to PWMB2,
– The counter register (PWMC) is initialized to 0x0001,
– The control logic and state sequencer are reset,
– The FLAG bit is set, and
– The output flip-flop is set if the new value in PWMB2 is different from 0x0000.
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Table 13-15 PWMSIC Bit Settings
Go to: www.freescale.com
Rev. 25 June 03
Description
MOTOROLA
13-46