MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 467

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.7.4 PWMSM Pulse Width Registers and Comparator
13.7.5 0% and 100% ‘Pulses’
MC68F375
REFERENCE MANUAL
The pulse width section of the PWMSM consists of two 16-bit pulse width registers
(PWMB1 and PWMB2) and one 16-bit comparator. PWMB2 holds the current PWM
pulse width value and PWMB1 holds the next PWM pulse width value. The software
establishes the next pulse width of the output PWM signal by writing a value into
PWMB1. Software may write a new pulse width value into PWMB1 at any time and this
new value will take effect at the start of the next PWM period (or when the LOAD bit in
the PWMSIC register is written to a ‘1’). The PWMSM hardware does not modify the
contents of PWMB1 at any time.
PWMB2 acts as a double buffer of PWMB1, allowing the contents of PWMB1 to be
changed at any time without affecting the current pulse width of the output signal; it
cannot be accessed directly by the software. PWMB1 can be read or written at any
time. The new value in the PWMB1 register is transferred to PWMB2 on the next full
cycle of the output or when a ‘1’ is written to the LOAD bit in the PWM SIC register .
The pulse width comparator is a 16-bit ‘ones-equality’ comparator that compares the
contents of the PWMB2 register with the 16-bit PWM counter. When the counter
reaches the value in PWMB2, a match occurs and the output flip-flop is cleared. This
pulse width match completes the pulse width; it does not affect the counter. Since a
‘ones-equality’ comparator is used, subsequent comparisons can occur, but will have
no effect on the output signal as the output flip-flop has already been cleared.
The PWM output pulse may be as short as one PWM clock period (PWMB2 = 0x0001).
It may be as long as one PWM clock period less than the PWM period; for example,
the pulse width equal to 65535 PWM clock periods can be obtained by setting PWMB2
= 0xFFFF and PWMA2 = 0x0000.
The 0% and 100% ‘pulses’ are special limiting cases (zero width and infinite width) that
are defined by the ‘always clear’ and ‘always set’ states of the output flip-flop.
The 0% pulse is generated by making the pulse width value in PWMB2 equal to
0x0000. The output is a true steady state signal with no glitches.
The 100% pulse is created by making the pulse width value in PWMB2 equal to or
greater than the period value in PWMA2. The output is a true steady state signal with
no glitches.
It is not possible to have a 100% duty cycle when the output period is selected to be
65536 PWM clock periods (by setting PWMB2 = 0x0000); in this case the maximum
duty cycle is 99.998% (100 x 65535/65536).
A value of 0x0002 in the period register and a value of 0x0001 in the
pulse register are the conditions necessary to obtain the maximum
possible output frequency for a given PWM clock period.
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Go to: www.freescale.com
Rev. 25 June 03
NOTE
MOTOROLA
13-41