MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 221

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

5.12.10 Conversion Command Word Table
MC68F375
REFERENCE MANUAL
Bit(s)
15:14
13:8
7:6
5:0
The CCW table is a RAM, 64 words long and 10 bits wide, which can be programmed
by the software to request conversions of one or more analog input channels. The
entries in the CCW table are 10-bit conversion command words. The CCW table is
written by software and is not modified by the QADC64. Each CCW requests the con-
version of an analog channel to a digital result. The CCW specifies the analog channel
number, the input sample time, and whether the queue is to pause after the current
CCW.
The ten implemented bits of the CCW word are read/write data. They may be written
when the software initializes the QADC64. Unimplemented bits are read as zeros, and
write operations have no effect. Each location in the CCW table corresponds to a loca-
tion in the result word table. When a conversion is completed for a CCW entry, the 10-
bit result is written in the corresponding result word entry. The QADC64 provides 64
CCW table entries.
The beginning of queue 1 is always the first location in the CCW table. The first loca-
tion of queue 2 is specified by the beginning of queue 2 pointer (BQ2) in QACR2. To
dedicate the entire CCW table to queue 1, software must do the following:
To dedicate the entire CCW table to queue 2, software must do the following:
• Program queue 2 to be in the disabled mode, and
• Program the beginning of BQ2 to
• Program queue 1 to be in the disabled mode
• Program BQ2 to be the first location in the CCW table.
CWPQ1
CWPQ2
Name
—
—
Reserved
Command word pointer for queue 1. This field is a software read-only field, and write operations
have no effect. CWPQ1 allows software to read the last executed CCW in queue 1, regardless
which queue is active. The CWPQ1 field is a CCW word pointer with a valid range of 0 to 63.
In contrast to CWP, CPWQ1 is updated when the conversion result is written. When the QADC64
finishes a conversion in queue 1, both the result register is written and the CWPQ1 are updated.
Finally, when queue 1 operation is terminated after a CCW is read that is defined as BQ2, CWP
points to BQ2 while CWPQ1 points to the last CCW queue 1.
During the stop mode, the CWPQ1 is reset to 63, since the control registers and the analog logic
are reset. When the freeze mode is entered, the CWPQ1 is unchanged; it points to the last exe-
cuted CCW in queue 1.
Reserved
Command word pointer for queue 2. This field is a software read-only field, and write operations
have no effect. CWPQ2 allows software to read the last executed CCW in queue 2, regardless
which queue is active. The CWPQ2 field is a CCW word pointer with a valid range of 0 to 63.
In contrast to CWP, CPWQ2 is updated when the conversion result is written. When the QADC64
finishes a conversion in queue 2, both the result register is written and the CWPQ2 are updated.
During the stop mode, the CWPQ2 is reset to 63, since the control registers and the analog logic
are reset. When the freeze mode is entered, the CWP is unchanged; it points to the last executed
CCW in queue 2.
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5-18 QASR1 Bit Settings
Go to: www.freescale.com
Rev. 25 June 03
64.
Description
MOTOROLA
5-45