MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 402

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.6.6.4 Over Programming
10.6.7 Erase
10.6.7.1 Erase Sequence
MC68F375
REFERENCE MANUAL
Programming a CMFI bit without a program margin read after each program pulse or
exceeding the specified program times or voltages will result in an over programmed
state. Once a CMFI bit has been over programmed, data in the array block that is
located upon the same column shall be lost as the over programmed bit causes the
entire column to appear programmed. To restore an array block with an over pro-
grammed bit the block must be erased and reprogrammed.
To modify the charge stored in the isolated element of the CMFI bit from a logic 0 state
to a logic 1 state, an erase operation is required. The erase operation cannot change
the logic 1 state to a logic 0 state; this transition must be done by the program opera-
tion. In the CMFI EEPROM, erase is a bulk operation that shall affect the stored charge
of all the isolated elements in an array block. To make the CMFI module block-eras-
able, the array is divided into blocks that are physically isolated from each other. Each
of the array blocks may be erased in isolation or in any combination. The CMFI array
block size is fixed for all blocks in the module at 32 Kbytes and the module is com-
prised of 4, 6 or 8 blocks. If the CMFI EEPROM array is protected (PROTECT = 1),
the array will not be erased. Also, if PEEM = 0 no erase voltages will be applied to the
array and if B0EM = 0, no programming voltages will be applied to block 0.
The array blocks selected for erase operation are determined by BLOCK[7:0].
The CMFI EEPROM module requires a sequence of writes to the high voltage control
registers (CMFICTL1 and CMFICTL2) and an erase interlock write in order to enable
the high voltage to the array and shadow information for erase operation. The erase
sequence follows.
1. Write PROTECT = 0 to disable protection on the array.
2. Set the initial pulse width bit settings per
3. Using section
4. Execute an erase interlock write to any CMFI array location.
5. Write EHV = 1 in the CMFICTL2 register.
6. Read the CMFICTL1 register until HVS = 0.
7. Write EHV = 0 in the CMFICTL2 register.
8. To verify the erase operation, read all locations that are being erased, including
CLKPM, write the pulse width timing control fields for an erase pulse in the
CMFICTL1 register. Write the BLOCK[7:0] to select the blocks to be erased, PE
= 1 and SES = 1 in the CMFICTL2 register.
the shadow information if the block containing it is erased. Off-page reads are
erase margin reads that update the read page buffer. (See section
Erase Margin
Freescale Semiconductor, Inc.
Reads.) If all the locations read as erased, go to step 9.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
10.4.9 A Technique to Determine SCLKR, CLKPE, and
Go to: www.freescale.com
Rev. 25 June 03
Table
10-7.
MOTOROLA
10.6.7.2
10-32