MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 452

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.5.2.1 Disable (DIS) mode
13.5.2.2 Input Pulse Width Measurement (IPWM) Mode
MC68F375
REFERENCE MANUAL
DIS mode is selected by making MODE[3:0] = 0000.
In this mode, all input capture and output compare functions of the DASM are disabled
and the FLAG bit is maintained in its reset state, but the input port pin function remains
available. The associated pin becomes a high impedance input and the input level on
this pin is reflected by the state of the IN bit in the DASMSIC register. All control and
interrupt bits remain accessible, allowing the software to prepare for future mode
selection. Data registers A and B are accessible at consecutive addresses. Writing to
data register B stores the same value in registers B1 and B2.
IPWM mode is selected by making MODE[3:0] = 0001.
This mode allows the width of a positive or negative pulse to be determined by captur-
ing the leading edge of the pulse on channel B and the trailing edge of the pulse on
channel A; successive captures are done on consecutive edges of opposite polarity.
The edge sensitivity is selected by the EDPOL bit in the DASMSIC register.
This mode also allows the software to determine the logic level on the input pin at any
time by reading the IN bit in the DASMSIC register.
The channel A input capture function remains disabled until the first rising edge trig-
gers the first input capture on channel B. When this rising edge is detected, the count
value of the time base bus selected by the BSL bit is latched in the 16-bit data register
B1; the FLAG bit is not affected. When the next falling edge is detected, the count
value of the time base bus is latched into the 16-bit data register A and, at the same
time, the FLAG bit is set and the contents of register B1 are transferred to register B2.
Reading data register B returns the value in register B2. If subsequent input capture
events occur while the FLAG bit is set, data registers A and B will be updated with the
latest captured values and the FLAG bit will remain set.
4. Re-enable DASM interrupts (if desired)
When changing between output modes (OP, OC or OCT), it is not
necessary to follow this procedure, as in these modes the FLAG bit
merely indicates to the software that the compare value can be
updated.
When changing modes, it is imperative to go through the DIS mode
in order to reset the DASM’s internal functions properly. Failure to do
this could lead to invalid and unexpected output compare or input
capture results, and to flags being set incorrectly.
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Go to: www.freescale.com
Rev. 25 June 03
WARNING
NOTE
MOTOROLA
13-26