MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 256

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.7.2.1 Receive RAM
6.7.2.2 Transmit RAM
6.7.2.3 Command RAM
MC68F375
REFERENCE MANUAL
Data received by the QSPI is stored in this segment, to be read by the CPU. Data
stored in the receive RAM is right-justified, i.e., the least significant bit is always in the
right-most bit position within the word regardless of the serial transfer length. Unused
bits in a receive queue entry are set to zero by the QSPI upon completion of the indi-
vidual queue entry. The CPU can access the data using byte, half-word, or word
addressing.
The CPTQP value in SPSR shows which queue entries have been executed. The CPU
uses this information to determine which locations in receive RAM contain valid data
before reading them.
Data that is to be transmitted by the QSPI is stored in this segment. The CPU normally
writes one word of data into this segment for each queue command to be executed. If
the corresponding peripheral, such as a serial input port, is used solely to input data,
then this segment does not need to be initialized.
Data must be written to transmit RAM in a right-justified format. The QSPI cannot mod-
ify information in the transmit RAM. The QSPI copies the information to its data
serializer for transmission. Information remains in transmit RAM until overwritten.
Command RAM is used by the QSPI in master mode. The CPU writes one byte of con-
trol information to this segment for each QSPI command to be executed. The QSPI
cannot modify information in command RAM.
Command RAM consists of 32 bytes. Each byte is divided into two fields. The periph-
eral chip-select field, enables peripherals for transfer. The command control field
provides transfer options.
0xYF FD40
0xYF FD7F
Half-Word
Receive
RAM
RRD
RRE
RRF
RR0
RR1
RR2
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
0xYF FDBF
0xYF FD80
Figure 6-3 QSPI RAM
Go to: www.freescale.com
Rev. 25 June 03
Half-Word
Transmit
RAM
TRD
TRE
TR0
TR1
TR2
TRF
0xYF FDDF
0xYF FDC0
Command
RAM
CRD
CR0
CR1
CR2
CRE
CRF
Byte
MOTOROLA
6-22