MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 215

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
12:8
7:0
15
14
13
Name
SSE1
CIE1
PIE1
MQ1
—
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
MQ1
Queue 1 completion interrupt enable. CIE1 enables completion interrupts for queue 1. The inter-
rupt request is generated when the conversion is complete for the last CCW in queue 1.
0 = Queue 1 completion interrupts disabled.
1 = Generate an interrupt request after completing the last CCW in queue 1.
Queue 1 pause interrupt enable. PIE1 enables pause interrupts for queue 1. The interrupt
request is generated when the conversion is complete for a CCW that has the pause bit set.
0 = Queue 1 pause interrupts disabled.
1 = Generate an interrupt request after completing a CCW in queue 1 which has the pause bit set.
Queue 1 single-scan enable. SSE1 enables a single-scan of queue 1 after a trigger event occurs.
The SSE1 bit may be set to a one during the same write cycle that sets the MQ1 bits for the sin-
gle-scan queue operating mode. The single-scan enable bit can be written as a one or a zero,
but is always read as a zero.
The SSE1 bit allows a trigger event to initiate queue execution for any single-scan operation on
queue 1. The QADC64 clears SSE1 when the single-scan is complete.
Queue 1 operating mode. The MQ1 field selects the queue operating mode for queue 1.
5-13
Reserved
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
shows the different queue 1 operating modes.
Freescale Semiconductor, Inc.
Table 5-13 Queue 1 Operating Modes
For More Information On This Product,
Disabled mode, conversions do not occur
Software triggered single-scan mode (started with SSE1)
External trigger rising edge single-scan mode
External trigger falling edge single-scan mode
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
External gated single-scan mode (started with SSE1)
Reserved mode
Software triggered continuous-scan mode
External trigger rising edge continuous-scan mode
External trigger falling edge continuous-scan mode
Periodic timer continuous-scan mode: time = QCLK period x 2
Table 5-12 QACR1 Bit Settings
Go to: www.freescale.com
Rev. 25 June 03
Operating Modes
Description
7
8
9
10
11
12
13
14
15
16
17
7
MOTOROLA
Table
5-39