MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 351

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
14:13
12:11
15
10
9
8
7
6
5
TCR1P
TCR2P
Name
STOP
T2CG
SUPV
PSCK
TPU3
EMU
STF
Low-power stop mode enable. If the STOP bit in TPUMCR is set, the TPU3 shuts down its inter-
nal clocks, shutting down the internal microengine. TCR1 and TCR2 cease to increment and
retain the last value before the stop condition was entered. The TPU3 asserts the stop flag (STF)
in TPUMCR to indicate that it has stopped.
0 = Enable TPU3 clocks
1 = Disable TPU3 clocks
Timer count register 1 prescaler control. TCR1 is clocked from the output of a prescaler. The
prescaler divides its input by 1, 2, 4, or 8. This is a write-once field unless the PWOD bit in
TPUMCR3 is set.
00 = Divide by 1
01 = Divide by 2
10 = Divide by 4
11 = Divide by 8
Refer to
Timer count register 2 prescaler control. TCR2 is clocked from the output of a prescaler. The
prescaler divides this input by 1, 2, 4, or 8. This is a write-once field unless the PWOD bit in
TPUMCR3 is set.
00 = Divide by 1
01 = Divide by 2
10 = Divide by 4
11 = Divide by 8
Refer to
Emulation control. In emulation mode, the TPU3 executes microinstructions from DPTRAM
exclusively. Access to the DPTRAM via the IMB3 is blocked, and the DPTRAM is dedicated for
use by the TPU3. After reset, this bit can be written only once.
0 = TPU3 and DPTRAM operate normally
1 = TPU3 and DPTRAM operate in emulation mode
TCR2 clock/gate control
0 = TCR2 pin used as clock source for TCR2
1 = TCR2 pin used as gate of DIV8 clock for TCR2
Refer to
Stop flag.
0 = TPU3 is operating normally
1 = TPU3 is stopped (STOP bit has been set)
Supervisor data space
0 = Assignable registers are accessible from user or supervisor privilege level
1 = Assignable registers are accessible from supervisor privilege level only
Standard prescaler clock. Note that this bit has no effect if the extended prescaler is selected
(EPSCKE = 1).
0 = f
1 = f
TPU3 enable. The TPU3 enable bit provides compatibility with the TPU. If running TPU code on
the TPU3, the microcode size should not be greater than 2 Kbytes and the TPU3 enable bit
should be cleared to zero. The TPU3 enable bit is write-once after reset. The reset value is one,
meaning that the TPU3 will operate in TPU3 mode.
0 = TPU mode; zero is the TPU reset value
1 = TPU3 mode; one is the TPU3 reset value
NOTE: The programmer should not change this value unless necessary when developing cus-
tom TPU microcode.
SYS
SYS
Freescale Semiconductor, Inc.
8.3.8 Prescaler Control for TCR1
8.3.9 Prescaler Control for TCR2
8.3.9 Prescaler Control for TCR2
32 is input to TCR1 prescaler, if standard prescaler is selected
4 is input to TCR1 prescaler, if standard prescaler is selected
For More Information On This Product,
Table 8-6 TPUMCR Bit Settings
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
Rev. 25 June 03
Description
for more information.
for more information.
for more information.
MOTOROLA
8-11