MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 252

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.7.1.2 QSPI Control Register 1
SPCR1 — QSPI Control Register 1
6.7.1.3 QSPI Control Register 2
MC68F375
REFERENCE MANUAL
RESET:
Bit(s)
14:8
MSB
SPE
7:0
15
15
0
SPCR1 enables the QSPI and specifies transfer delays. The CPU has read/write
access to SPCR1, but the QSPI has read access only to all bits except SPE. SPCR1
must be written last during initialization because it contains SPE. The QSPI automati-
cally clears this bit after it completes all serial transfers or when a mode fault occurs.
Writing a new value to SPCR1 while the QSPI is enabled disrupts operation.
SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt
enable bit. The CPU has read/write access to SPCR2, but the QSPI has read access
only. Writes to this register are buffered. New SPCR2 values become effective only
after completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes
execution to restart at the designated location. Reads of SPCR2 return the current
value of the register, not the buffer.
14
DSCKL
0
Name
SPE
DTL
13
0
QSPI enable. Refer to
0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.
1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.
Delay before SCK. When the DSCK bit is set in a command RAM byte, this field determines the
length of the delay from PCS valid to SCK transition. The following equation determines the
actual delay before SCK:
where DSCKL equals is in the range of 1 to 127.
Refer to
Length of delay after transfer. When the DT bit is set in a command RAM byte, this field deter-
mines the length of the delay after a serial transfer. The following equation is used to calculate
the delay:
where DTL is in the range of 1 to 255.
A zero value for DTL causes a delay-after-transfer value of 8192
MHz system clock).
Refer to
12
0
Freescale Semiconductor, Inc.
DSCKL
6.7.5.3 Delay Before Transfer
6.7.5.4 Delay After Transfer
QUEUED SERIAL MULTI-CHANNEL MODULE
11
For More Information On This Product,
0
Table 6-15 SPCR1 Bit Settings
10
1
Go to: www.freescale.com
6.7.4.1 Enabling, Disabling, and Halting the
9
0
Rev. 25 June 03
8
0
Delay after Transfer
PCS to SCK Delay
for more information.
7
0
for more information.
Description
6
0
5
0
=
=
32
------------------------ -
DSCKL
------------------- -
f SYS
f
SYS
4
0
DTL
DTL
f
SYS
3
0
SPI.
(204.8 µ s with a 40-
2
1
0xYF FC1A
MOTOROLA
1
0
LSB
6-18
0
0