MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 326

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

7.8 Programmer’s Model
MC68F375
REFERENCE MANUAL
Each one of the 16 message buffers can be an interrupt source, if its corresponding
IMASK bit is set. There is no distinction between transmit and receive interrupts for a
particular buffer. Each of the buffers is assigned a bit in the IFLAG register. An IFLAG
bit is set when the corresponding buffer completes a successful transmission/recep-
tion. An IFLAG bit is cleared when the CPU32 reads IFLAG while the associated bit is
set, and then writes it back as zero (and no new event of the same type occurs
between the read and the write actions).
The other three interrupt sources (bus off, error and wake up) act in the same way, and
have flag bits located in the error and status register (ESTAT). The bus off and error
interrupt mask bits (BOFFMSK and ERRMSK) are located in CANCTRL0, and the
wake up interrupt mask bit (WAKEMSK) is located in the module configuration regis-
ter.
addresses.
Table 7-10
CAN modules in the MC68F375 address map.
The column labeled “Access” indicates the privilege level at which the CPU must be
operating to access the register. A designation of “S” indicates that supervisor mode
is required. A designation of “S/U” indicates that the register can be programmed for
either supervisor mode access or unrestricted access.
Table 7-9
shows the TouCAN address map. Refer to
Table 7-9 Interrupt Sources and Vector Addresses
Interrupt Source
shows TouCAN interrupt priorities and their corresponding vector
Buffer 10
Buffer 11
Buffer 12
Buffer 13
Buffer 14
Buffer 15
Wake-up
Buffer 0
Buffer 1
Buffer 2
Buffer 3
Buffer 4
Buffer 5
Buffer 6
Buffer 7
Buffer 8
Buffer 9
Bus off
Error
Freescale Semiconductor, Inc.
For More Information On This Product,
CAN 2.0B CONTROLLER MODULE
Go to: www.freescale.com
Rev. 25 June 03
0bXXX00000 (Highest priority)
0bXXX10010 (Lowest priority)
Vector Number
0bXXX00001
0bXXX00010
0bXXX00011
0bXXX00100
0bXXX00101
0bXXX00110
0bXXX00111
0bXXX01000
0bXXX01001
0bXXX01010
0bXXX01011
0bXXX01100
0bXXX01101
0bXXX01110
0bXXX01111
0bXXX10000
0bXXX10001
Figure 1-2
to locate the Tou-
MOTOROLA
7-20