MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 250

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.7.1.1 QSPI Control Register 0
SPCR0 — QSPI Control Register 0
MC68F375
REFERENCE MANUAL
RESET:
MSTR
Access
NOTES:
MSB
15
0
To ensure proper operation, set the QSPI enable bit (SPE) in SPCR1 only after initial-
izing the other control registers. Setting this bit starts the QSPI.
Rewriting the same value to a control register does not affect QSPI operation with the
exception of writing NEWQP in SPCR2. Rewriting the same value to these bits causes
the RAM queue pointer to restart execution at the designated location.
Before changing control bits, the user should halt the QSPI. Writing a different value
into a control register other than SPCR2 while the QSPI is enabled may disrupt oper-
ation. SPCR2 is buffered, preventing any disruption of the current serial transfer. After
the current serial transfer is completed, the new SPCR2 value becomes effective.
SPCR0 contains parameters for configuring the QSPI before it is enabled. The CPU
has read/write access to SPCR0, but the QSPI has read access only. SPCR0 must be
initialized before QSPI operation begins. Writing a new value to SPCR0 while the
QSPI is enabled disrupts operation.
S/U
S/U
S/U
S/U
S/U
S/U
S/U
1. S = Supervisor access only
2. 8-bit registers, such as SPCR3 and SPSR, are on 8-bit boundaries. 16-bit registers such as SPCR0 are on 16-
S/U = Supervisor access only or unrestricted user access (assignable data space).
bit boundaries.
1
WOM
14
Q
0
0xYF FDC0 –
0xYF FD40 –
0xYF FD80 –
0xYF FC1E/
0xYF FDDF
0xYF FC1A
0xYF FC1C
0xYF FDBF
0xYF FC18
0xYF FC1F
0xYF FD7F
Address
13
0
12
0
BITS
Freescale Semiconductor, Inc.
MSB
QUEUED SERIAL MULTI-CHANNEL MODULE
11
For More Information On This Product,
0
See
QSPI Control Register 3 (SPCR3)
2
Table 6-12 QSPI Register Map
Table 6-17
10
0
Go to: www.freescale.com
CPOL CPHA
9
0
Rev. 25 June 03
for bit descriptions.
8
1
Transmit Data RAM (32 half-words)
See
See
See
Receive Data RAM (32 half-words)
QSPI Control Register 0 (SPCR0)
QSPI Control Register 1 (SPCR1)
QSPI Control Register 2 (SPCR2)
Command RAM (32 bytes)
Table 6-13
Table 6-15
Table 6-16
7
0
6
0
for bit descriptions.
for bit descriptions.
for bit descriptions.
5
0
See
QSPI Status Register (SPSR)
Table 6-18
4
0
SPBR
3
0
for bit descriptions.
2
1
0xYF FC18
MOTOROLA
1
0
LSB
LSB
6-16
0
0