MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 168

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Following reset, the MCU fetches initialization values from the reset vector, beginning
at 0x000000 in supervisor program space. The CSBOOT chip-select signal is enabled
and can select an external boot device mapped to a base address of 0x000000.
The MSB of the CSBTPA field in CSPAR0 has a reset value of one, so that chip-select
function is selected by default out of reset. The BYTE field in chip-select option register
CSORBT has a reset value of “both bytes” so that the select signal is enabled out of
reset. The LSB of the CSBOOT field, determined by the logic level of DATA0 during
reset, selects the boot ROM port size. When DATA0 is held low during reset, a port
size of eight bits is selected. When DATA0 is held high during reset, a port size of 16
bits is selected. DATA0 has a weak internal pull-up device, so that a 16-bit port is
selected by default out of reset. As mentioned above, the internal pull-up device can
be overcome by bus loading effects. To ensure a particular configuration out of reset,
use a pull-up resistor or an active device to place DATA0 in a known state during reset.
The base address field in the boot chip-select base address register CSBARBT has a
reset value of all zeros, so that when the initial access to address 0x000000 is made,
an address match occurs, and the CSBOOT signal is asserted. The block size field in
CSBARBT has a reset value of 0b111 (one Mbyte on CPU32-based MCUs and 512
Kbytes on CPU16-based MCUs).
Table 4-40 Chip-Select Base and Option Register
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
Async/sync Mode
Upper/lower byte
Address space
For More Information On This Product,
Base address
Read/write
Autovector
Block size
DSACK
AS/DS
Fields
IPL
Go to: www.freescale.com
Reset Values
Rev. 25 June 03
Table 4-41
External interrupt vector
Asynchronous mode
Reset Values
No wait states
shows CSBOOT reset values.
CPU space
0x000000
Any level
2 Kbytes
Disabled
Disabled
AS
MOTOROLA
4-86