MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 74

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

3.10.3 Enabling BDM
3.10.4 BDM Sources
MC68F375
REFERENCE MANUAL
Accidentally entering BDM in a non-development environment can lock up the CPU32
when the serial command interface is not available. For this reason, BDM is enabled
during reset via the breakpoint (BKPT) signal.
BDM operation is enabled when BKPT is asserted (low) at the rising edge of RESET.
BDM remains enabled until the next system reset. A high BKPT signal on the trailing
edge of RESET disables BDM. BKPT is latched again on each rising transition of
RESET. BKPT is synchronized internally, and must be held low for at least two clock
cycles prior to negation of RESET.
BDM enable logic must be designed with special care. If hold time on BKPT (after the
trailing edge of RESET) extends into the first bus cycle following reset, the bus cycle
could inadvertently be tagged with a breakpoint. Refer to the SCIM Reference Manual
(SCIMRM/AD) for timing information.
Once BDM is enabled, any of several sources can cause the transition from normal
mode to BDM. These sources include external breakpoint hardware, the BGND
instruction, a double bus fault, and internal peripheral breakpoints. If BDM is not
enabled when an exception condition occurs, the exception is processed normally.
TARGET
SYSTEM
TARGET
SYSTEM
Figure 3-8 Common In-Circuit Emulator Diagram
Figure 3-9 Bus State Analyzer Configuration
Freescale Semiconductor, Inc.
For More Information On This Product,
TARGET
MCU
CENTRAL PROCESSOR UNIT
Go to: www.freescale.com
Rev. 25 June 03
IN-CIRCUIT
EMULATOR
TARGET
MCU
BUS STATE
ANALYZER
MOTOROLA
3-20
1128A
1129A