MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 50

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Address Bus
QADC64 Analog Input
QADC64 Analog Input
Analog MUX Inputs
Address Strobe
Autovector
Bus Error
Bus Grant
Bus Grant Acknowledge
Breakpoint
Bus Request
System Clock Out
TOUCAN Receive Data
TOUCAN Transmit Data
Chip Selects
Boot Chip Select
Emulator Chip Select
Module Chip Select
CTM PWM
CTM9 Double Action
Channel
CTM9 Modulus Clock
CTM9 Single Action Chan-
nels
Data Bus
Data Strobe
Data and Size
Acknowledge
Development Serial In, Out,
Clock
QADC64 External Trigger
Crystal Oscillator
VCO Reference Mode Se-
lect
Function Codes
Freeze
Halt
Instruction Pipeline
Signal Name
DSI, DSO, DSCLK Serial I/O and clock for background debug mode
Freescale Semiconductor, Inc.
CS[10:5], CS[3],
CTS[20B - 14A]
AN[59:48]/[3:0]
EXTAL, XTAL
AN[z, y, x, w]
DSACK[1:0]
ADDR[23:0]
CPWM[8:5]
For More Information On This Product,
Mnemonic
DATA[15:0]
ETRIG[2:1]
ANX[15:0]
CTD[10:9]
FASTREF
CSBOOT
CLKOUT
FREEZE
BGACK
CTM2C
FC[2:0]
BERR
CNRX
AVEC
CNTX
BKPT
CS[0]
HALT
IPIPE
CSM
CSE
BG
BR
DS
AS
Table 2-5 Signal Functions
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SIGNAL DESCRIPTIONS
Rev. 25 June 03
24-bit address bus used by CPU32
Sixteen channel A/D converter analog input pins
Four input channels utilized when operating in multiplexed mode
Analog signal inputs multiplexed to the analog converters
Indicates that a valid address is on the address bus
Requests an automatic vector during interrupt acknowledge
Indicates that a bus error has occurred
Indicates that the MCU has relinquished the bus
Indicates that an external device has assumed bus mastership
Signals a hardware breakpoint to the CPU
Indicates that an external device requires bus mastership
Internal system clock
CAN 2.0B Serial Data Input
CAN 2.0B Serial Data Output
Select external devices at programmed addresses
Chip select for external boot start-up ROM
Chip select for external port emulator
Chip select for external ROM emulator
PWM channels which can also be used as general-purpose output
pins
Bidirectional CTM9 double action timer channels
CTM9 modulus counter clock input
Bidirectional CTM9 single action timer channels
16-bit data bus
Read cycle — indicates that an external device should place valid
data on the data bus. Write cycle — indicates that valid data is on
the data bus.
Provides asynchronous data transfers and dynamic bus sizing
When a scan queue is in external trigger mode, the corresponding
ETRIG pin is configured as a digital input and the software pro-
grammed I/O direction in the DDR is ignored.
Connections for clock synthesizer circuit reference; a crystal or an
external oscillator can be used
Selects between FAST or SLOW reference modes
Identify processor state and current address space
Indicates that the CPU has acknowledged a breakpoint
Suspend external bus activity
Indicates instruction pipeline activity
Function
MOTOROLA
2-6