MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 271

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.7.5.7 Master Wraparound Mode
6.7.6 Slave Mode
MC68F375
REFERENCE MANUAL
of the bit in PORTQS that corresponds to the chip-select pin determines the base state
of the chip-select signal. If the base state is zero, chip-select assertion must be active
high (PCS bit in command RAM must be set); if base state is one, assertion must be
active low (PCS bit in command RAM must be cleared). PORTQS bits are cleared dur-
ing reset. If no new data is written to PORTQS before pin assignment and
configuration as an output, the base state of chip-select signals is zero and chip-select
pins are configured for active-high operation.
Wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can wrap
to pointer address 0x0 or to the address pointed to by NEWQP, depending on the state
of the WRTO bit in SPCR2.
In wraparound mode, the QSPI cycles through the queue continuously, even while the
QSPI is requesting interrupt service. SPE is not cleared when the last command in the
queue is executed. New receive data overwrites previously received data in receive
RAM. Each time the end of the queue is reached, the SPIF flag is set. SPIF is not auto-
matically reset. If interrupt-driven QSPI service is used, the service routine must clear
the SPIF bit to end the current interrupt request. Additional interrupt requests during
servicing can be prevented by clearing SPIFIE, but SPIFIE is buffered. Clearing it does
not end the current request.
Wraparound mode is exited by clearing the WREN bit or by setting the HALT bit in
SPCR3. Exiting wraparound mode by clearing SPE is not recommended, as clearing
SPE may abort a serial transfer in progress. The QSPI sets SPIF, clears SPE, and
stops the first time it reaches the end of the queue after WREN is cleared. After HALT
is set, the QSPI finishes the current transfer, then stops executing commands. After
the QSPI stops, SPE can be cleared.
Clearing the MSTR bit in SPCR0 selects slave mode operation. In slave mode, the
QSPI is unable to initiate serial transfers. Transfers are initiated by an external SPI bus
master. Slave mode is typically used on a multi-master SPI bus. Only one device can
be bus master (operate in master mode) at any given time.
Before QSPI operation is initiated, QSMCM register PQSPAR must be written to
assign necessary pins to the QSPI. The pins necessary for slave mode operation are
MISO, MOSI, SCK, and PCS0/SS. MISO is used for serial data output in slave mode,
and MOSI is used for serial data input. Either or both may be necessary, depending
on the particular application. SCK is the serial clock input in slave mode and must be
assigned to the QSPI for proper operation. Assertion of the active-low slave select sig-
nal SS initiates slave mode operation.
Before slave mode operation is initiated, DDRQS must be written to direct data flow
on the QSPI pins used. Configure the MOSI, SCK and PCS0/SS pins as inputs. The
MISO pin must be configured as an output.
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
6-37