MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 101

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.3.8.1 POR Characteristics
4.3.8.2 External Clock Operating Mode
4.3.8.3 PLL Operating Mode
4.3.8.4 RSTEN Bit Operation
4.3.8.5 Reset Conditions
MC68F375
REFERENCE MANUAL
The LOC detector operates in either PLL or external clock modes. When it is triggered,
limp mode is entered, the SLIMP bit is set, and an alternate clock is provided as the
system clock until edges are detected on the crystal/external clock input. The alternate
clock is the output of an RC oscillator which is also used as the time-base for the LOC
detector. All clock switching is done synchronously, such that no short pulses, or
glitches, are caused on the system clock.
When the power-on-reset logic detects the application of power or the return of power
after a power loss situation, the internal RC oscillator is selected as the system clock
source. The RC oscillator begins to operate at relatively low levels of VDD and typically
several milliseconds before the crystal oscillator/VCO will begin to function. This pro-
vides system clocks as soon as possible, allowing I/O pins and modules to reach
defined reset states as soon as possible. After the crystal oscillator and VCO start-up
is recognized by the LOC logic, a few more RC clock edges followed by a few VCO
clock edges will switch the system clock source control logic over from the RC oscilla-
tor to the crystal oscillator/VCO subsystem. Exact switching time depends on the RC
oscillator frequency and the crystal/VCO clock frequency.
If SCIMCLK stops in external clock mode, the LOC detect triggers, and the system
clock is switched to the alternate clock until the external clock input restarts.
When the PLL is being used to provide the system clock and the crystal reference
input stops, the synthesized clock frequency will drop below the LOC threshold. When
this occurs, the system clock source is switched to the alternate clock until the crystal
reference restarts. If and when the crystal restarts, the clock source will switch back to
the PLL, in unlocked mode. The PLL will then relock to the reference frequency.
The RSTEN bit is used to put the part in reset if loss of clock is detected. The reset
sequence clears the RSTEN bit, and when the sequence finishes, the part exits reset
and runs in limp mode. Setting the RSTEN bit while in limp mode will cause reset
immediately. This will allow for a continuously reset the part as long as it is in limp
mode, by setting the RSTEN bit after exiting reset.
To save power, the RC oscillator can be disabled by setting the LOSCD bit in the
SYNCR register. In this case, the ability to detect loss of clock is disabled. However, if
the RESET pin is driven low, the RC oscillator is forced on to provide a system clock,
ensuring that external RESET will be recognized even in a DC state. For more infor-
mation, see
4.7
Reset.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
4-19