MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 338

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
5:4
8
7
6
3
2
1
0
RXWARN
WAKEINT
BOFFINT
ERRINT
TX/RX
Name
IDLE
FCS
—
BITERR[1:0]
00
01
10
11
Receiver error status flag. The RXWARN status flag reflects the status of the TouCAN
receive error counter.
0 = Receive error counter
1 = Receive error counter
Idle status. The IDLE bit indicates when there is activity on the CAN bus.
0 = The CAN bus is not idle.
1 = The CAN bus is idle.
Transmit/receive status. The TX/
or receiving a message. TX/
0 = The TouCAN is receiving a message if IDLE = 0.
1 = The TouCAN is transmitting a message if IDLE = 0.
Fault confinement state. The FCS[1:0] field describes the state of the TouCAN. Refer to
Table
If the SOFTRST bit in CANMCR is asserted while the TouCAN is in the bus off state, the
error and status register is reset, including FCS[1:0]. However, as soon as the TouCAN exits
reset, FCS[1:0] bits will again reflect the bus off state. Refer to
more information on entry into and exit from the various fault confinement states.
Reserved
Bus off interrupt. The BOFFINT bit is used to request an interrupt when the TouCAN enters
the bus off state.
0 = No bus off interrupt requested.
1 = When the TouCAN state changes to bus off, this bit is set, and if the BOFFMSK bit in
transmit or receive error.
0 = No error interrupt request.
1 = If an event which causes one of the error bits in the error and status register to be set
To clear this bit, first read it as a one, then write as a zero. Writing a one has no effect.
Wake interrupt. The WAKEINT bit indicates that bus activity has been detected while the
TouCAN module is in low-power stop mode.
0 = No wake interrupt requested.
1 = When the TouCAN is in low-power stop mode and a recessive to dominant transition is
Error Interrupt. The ERRINT bit is used to request an interrupt when the TouCAN detects a
Table 7-21 ESTAT Bit Settings (Continued)
CANCTRL0 is set, an interrupt request is generated. This interrupt is not requested after
reset.
occurs, the error interrupt bit is set. If the ERRMSK bit in CANCTRL0 is set, an interrupt
request is generated.
detected on the CAN bus, this bit is set. If the WAKEMSK bit is set in CANMCR, an in-
terrupt request is generated.
Freescale Semiconductor, Inc.
7-23.
Table 7-22 Transmit Bit Error Status
For More Information On This Product,
No transmit bit error
At least one bit sent as dominant was received as recessive
At least one bit sent as recessive was received as dominant
Not used
CAN 2.0B CONTROLLER MODULE
Go to: www.freescale.com
Rev. 25 June 03
96.
96.
RX
RX
has no meaning when IDLE = 1.
Bit Error Status
bit indicates when the TouCAN module is transmitting
Description
7.4.4 Error Counters
MOTOROLA
for
7-32