MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 445

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.4.2 SASM Interrupts
13.4.3 Freeze Action on the SASM
13.4.4 SASM Registers
MC68F375
REFERENCE MANUAL
reset by software (see
is serviced, the FLAG bit should be cleared by the servicing routine before returning
from that routine. If a subsequent output compare occurs while the FLAG bit is set, the
internal output compare functions normally, and the FLAG bit remains set.
In OP mode, the IN bit value reflects the logic state on the output of the output flip-flop.
Each channel in the dual-channel SASM has separately enabled and initiated inter-
rupts and they each have their own unique vector number and address. However, they
are both assigned to the same interrupt level and arbitration priority by the IL[2:0] and
IARB3 bits in the SICA register.
A valid SASM interrupt is recognized when the FLAG bit is set, the corresponding IEN
bit is set and the interrupt level defined by bits IL[2:0] is not equal to zero.
The FLAG bit is a status bit that indicates, when set, that an input capture or output
compare has occurred on the corresponding single action channel.
The relative priority of these sources of interrupt is fixed and channel A has a higher
priority than channel B.
When the IMB FREEZE signal is recognized, the SASM input capture and output com-
pare functions are halted. As soon as the FREEZE signal is negated, SASM actions
resume as if nothing had happened. During freeze, the IN bits of the SIC registers
(SICA and SICB) are readable and return the levels present at the input pins if an input
mode is in operation, or the output value if an output mode is in operation (see
SICA — SASM Status/Interrupt Control Register A
Status/Interrupt Control Register
the force output function remains available, allowing the software to output the desired
level (a useful feature for debugging). All SASM registers are accessible during freeze.
The SASM register map comprises eight 16-bit register locations. As shown in
13-6, the register block contains two SASM registers for each channel and four
reserved registers. All unused bits and reserved address locations return zero when
read by the software. Writing to unused bits and reserved address locations has no
meaning nor effect. All register addresses in this section are specified as offsets from
the base address of the SASM. In CTM implementations featuring multiple SASMs,
each SASM has its own set of registers.
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
13.4.1.1 Clearing and Using the FLAG
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Rev. 25 June 03
B). When one of the output modes is in operation,
and
13.4.4.3 SICB — SASM
Bits). If the interrupt
MOTOROLA
13.4.4.1
Table
13-19