MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 273

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.7.6.1 Description of Slave Operation
MC68F375
REFERENCE MANUAL
After reset, the QSMCM registers and the QSPI control registers must be initialized as
described above. Although the command control segment is not used, the transmit
and receive data segments may, depending upon the application, need to be initial-
ized. If meaningful data is to be sent out from the QSPI, the user should write the data
to the transmit data segment before enabling the QSPI.
If SPE is set and MSTR is not set, a low state on the slave select (PCS0/SS) pin com-
mences slave mode operation at the address indicated by NEWQP. The QSPI
transmits the data found in the transmit data segment at the address indicated by
NEWQP, and the QSPI stores received data in the receive data segment at the ad-
dress indicated by NEWQP. Data is transferred in response to an external slave clock
input at the SCK pin.
Because the command control segment is not used, the command control bits and
peripheral chip-select codes have no effect in slave mode operation. The QSPI does
not drive any of the four peripheral chip-selects as outputs. PCS0/SS is used as an
input.
Although CONT cannot be used in slave mode, a provision is made to enable receipt
of more than 16 data bits. While keeping the QSPI selected (PCS0/SS is held low), the
QSPI stores the number of bits, designated by BITS, in the current receive data seg-
ment address, increments NEWQP, and continues storing the remaining bits (up to the
BITS value) in the next receive data segment address.
As long as PCS0/SS remains low, the QSPI continues to store the incoming bit stream
in sequential receive data segment addresses, until either the value in BITS is reached
or the end-of-queue address is used with wraparound mode disabled.
When the end of the queue is reached, the SPIF flag is asserted, optionally causing
an interrupt. If wraparound mode is disabled, any additional incoming bits are ignored.
If wraparound mode is enabled, storing continues at either address 0x0 or the address
of NEWQP, depending on the WRTO value. When using this capability to receive a
long incoming data stream, the proper delay between transfers must be used. The
QSPI requires time, approximately 0.425 µs with a 40-MHz system clock, to prefetch
the next transmit RAM entry for the next transfer. Therefore, the user may select a
baud rate that provides at least a 0.6-µs delay between successive transfers to ensure
no loss of incoming data. If the system clock is operating at a slower rate, the delay
between transfers must be increased proportionately.
Because the BITSE option in the command control segment is no longer available,
BITS sets the number of bits to be transferred for all transfers in the queue until the
CPU changes the BITS value. As mentioned above, until PCS0/SS is negated
(brought high), the QSPI continues to shift one bit for each pulse of SCK. If PCS0/SS
is negated before the proper number of bits (according to BITS) is received, the next
time the QSPI is selected it resumes storing bits in the same receive-data segment
address where it left off. If more than 16 bits are transferred before negating the PCS0/
SS, the QSPI stores the number of bits indicated by BITS in the current receive data
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
6-39