MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 325

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

7.7 Interrupts
MC68F375
REFERENCE MANUAL
INTERRUPT
REQUEST
LEVEL
(ILCAN[2:0]
MASKS
BUFFER
INTERRUPTS
BUS OFF
ERROR
WAKE UP
VECTOR
BASE
ADDRESS
(IVBA[2:0])
While its clocks are stopped, if the TouCAN senses that any one of the aforementioned
conditions is no longer true, it restarts its clocks. The TouCAN then continues to mon-
itor these conditions and stops or restarts its clocks accordingly.
The TouCAN is capable of generating one interrupt level on the IMB3. This level is
programmed into the priority level bits in the interrupt configuration register (CANICR).
This value determines which interrupt signal is driven onto the bus when an interrupt
is requested.
When an interrupt is requested, the CPU32 initiates an IACK cycle. The TouCAN
decodes the IACK cycle and compares the CPU32 recognized level to the level that it
is currently requesting. If a match occurs, then arbitration begins. If the TouCAN wins
arbitration, it generates a uniquely encoded interrupt vector that indicates which event
is requesting service. This encoding scheme is as follows:
Figure 7-5
• No CPU access to the TouCAN module.
• The TouCAN is not in debug mode, low-power stop mode, or the bus off state.
• The higher-order bits of the interrupt vector come from the IVBA[2:0] field in CAN-
• The low-order five bits are an encoded value that indicate which of the 19 Tou-
frame awaiting transmission in any message buffer.
ICR.
CAN interrupt sources is requesting service.
shows a block diagram of the interrupt hardware.
Figure 7-5 TouCAN Interrupt Vector Generation
19
16
Freescale Semiconductor, Inc.
For More Information On This Product,
CAN 2.0B CONTROLLER MODULE
INTERRUPT
Go to: www.freescale.com
ENABLE
LOGIC
Rev. 25 June 03
3
3
19
INTERRUPT
ENCODER
PRIORITY
INTERRUPT
DECODER
LEVEL
7
5
3
MODULE
INTERRUPT
VECTOR
TOUCAN INTERRUPT GEN
IRQ[7:1]
MOTOROLA
7-19