MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 144

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.7.8.2 Data Bus Mode Selection
MC68F375
REFERENCE MANUAL
as normal address bus pins in expanded operating modes. Refer to
Reduction in Single-Chip Mode
information on the address bus disable bit (ABD).
The ADDR[23:19] pins have multiple functions as high-order address lines, chip
selects, or discrete outputs and are configured differently depending on operating
mode selection and data bus conditioning when RESET is released. The following
paragraphs contain a summary of pin configuration options for each external bus
configuration.
DATA[15:0] have weak internal pull-up devices. When pins are held high by the inter-
nal pull-ups, the MCU uses a default operating configuration. Specific lines can be held
low externally during reset to achieve alternate configurations.
Use an active device to properly configure data bus lines while RESET is low. Data
bus configuration logic must release the bus before the first bus cycle after reset to
prevent conflict with external memory devices. The first bus cycle occurs ten CLKOUT
cycles after RESET is released. If external mode selection logic causes a conflict of
this type, an isolation resistor on the driven lines may be required.
a recommended method for conditioning the data bus mode select signals.
The mode configuration drivers are conditioned with R/W and DS to prevent conflicts
between external devices and the MCU when RESET is asserted. If RESET is
asserted during an external write cycle, R/W conditioning (as shown in
prevents corruption of the data during the write. Similarly, DS conditions the mode con-
figuration drivers so that external reads are not corrupted when RESET is asserted
during an external read cycle.
External bus loading can overcome the weak internal pull-up devices
on data bus lines and hold pins low during reset.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
and
APPENDIX A INTERNAL MEMORY MAP
NOTE
Figure 4-19
Figure
4.2.4 Noise
MOTOROLA
shows
4-19)
4-62
for