MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 436

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.3.1 The MCSM Modulus Latch
13.3.2 The MCSM Counter
13.3.2.1 Loading the MCSM Counter Register
MC68F375
REFERENCE MANUAL
The main components of the MCSM are a 16-bit modulus latch, a 16-bit loadable up-
counter, counter loading logic, a clock selector, a time base bus driver and an interrupt
interface.
The 16-bit modulus latch is a read/write register that is used to reload the counter auto-
matically with a predetermined value. The contents of the modulus latch register can
be read at any time. Writing to the register loads the modulus latch with the new value.
This value is then transferred to the counter register on the next hardware load of that
counter. However, writing to the corresponding counter register loads the modulus
latch and the counter register immediately with the new value. The modulus latch reg-
ister is cleared to 0x0000 by reset.
The counter is composed of a 16-bit read/write register associated with a 16-bit incre-
menter. Reading the counter transfers the contents of the counter register to the data
bus; writing to the counter loads the modulus latch and the counter register immedi-
ately with the new value. The counter can be clocked with different clock sources (see
13.3.3 MCSM Clock
The counter register can be loaded by writing directly to it. The counter register is also
loaded from the modulus latch each time a counter overflow occurs and the COF flag
bit in the MCSM status/interrupt/control register (MCSMSIC) is set.
Loading of the counter register from the modulus register can also be triggered by an
external event on the modulus load pin CTML. The edge on the CTML pin that triggers
the loading of the counter register is selected by bits EDGEN and EDGEP in the
MCSMSIC register. Hardware is provided to prevent the occurrence of spurious edges
while changing the EDGEN and EDGEP bits. Reset clears the EDGEN and EDGEP
In order to be able to count, the MCSM requires the CPSM clock sig-
nals to be present. On coming out of reset, the MCSM will not count
internal or external events until the prescaler in the CPSM starts run-
ning (when the software sets the PRUN bit). This allows all counters
in the CTM submodules to be synchronized.
Reset presets the counter register to 0x0000. Writing 0x0000 to the
counter register while its value is 0xFFFF does not set the COF flag
and does not generate an interrupt.
When the modulus latch is loaded with 0xFFFF, the overflow flag is
set on every counter clock pulse.
Freescale Semiconductor, Inc.
Sources).
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Go to: www.freescale.com
Rev. 25 June 03
NOTE
NOTE
NOTE
MOTOROLA
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