MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 112

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.4.9 Low Power Stop Mode
4.4.9.1 Periodic Interrupt Control Register
MC68F375
REFERENCE MANUAL
Because of SCIM2E hardware prioritization, a PIT interrupt is serviced before an exter-
nal interrupt request of the same priority. The periodic timer continues to run when the
interrupt is disabled.
The PIV field contains the periodic interrupt vector. The vector is placed on the IMB
when an interrupt request is made. The vector number is used to calculate the address
of the appropriate vector in the exception vector table. The reset value of the PIV field
is 0x0F, which corresponds to the uninitialized interrupt exception vector.
When the CPU32 executes the LPSTOP instruction, the current interrupt priority mask
is stored in the clock control logic, internal clocks are disabled according to the state
of the STSCIM bit in SYNCR, and the MCU enters low power stop mode. The bus
monitor, halt monitor, and spurious interrupt monitor are all inactive during low power
stop.
During low power stop mode, the clock input to the software watchdog timer is dis-
abled and the timer stops. The software watchdog begins to run again on the first rising
clock edge after the MCU exits low power stop mode. The watchdog is not reset when
entering low power stop mode. A service sequence must be performed to reset the
timer.
The periodic interrupt timer does not respond to the LPSTOP instruction, but continues
to run during LPSTOP. To stop the periodic interrupt timer, PITM[7:0] must be loaded
with zero before entering LPSTOP. A PIT interrupt, or an external interrupt request,
can bring the MCU out of low power stop mode if it has a higher priority than the inter-
rupt mask value stored in the clock control logic when low power stop mode is entered.
LPSTOP can be terminated by a reset.
PICR sets the interrupt level and vector number for the periodic interrupt timer (PIT).
Bits [10:0] can be read or written at any time. Bits [15:11] are reserved and always read
zero.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
Table 4-14 Periodic Interrupt Priority
For More Information On This Product,
PIRQL[2:0]
000
001
010
011
100
101
110
111
Go to: www.freescale.com
Rev. 25 June 03
Periodic Interrupt Disabled
Interrupt Priority Level 1
Interrupt Priority Level 2
Interrupt Priority Level 3
Interrupt Priority Level 4
Interrupt Priority Level 5
Interrupt Priority Level 6
Interrupt Priority Level 7
Priority Level
MOTOROLA
4-30