MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 423

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

12.6.2 Bootstrap Operation
12.6.3 Normal Operation
12.6.4 Read/Write Access
MC68F375
REFERENCE MANUAL
Bootstrap mode will be disabled if STOP is set during master reset, regardless of the
default reset state of BOOT.
If BOOT = 0 in the ROMMCR, the ROM module may be used as a bootstrap ROM by
the system. The ROM module will only respond to the bootstrap addresses if the
STOP control bit in the ROMMCR register is a 0. If STOP is a 1, bootstrap addresses
will be ignored. Subsequently clearing the STOP bit will not cause the ROM to enter
bootstrap mode.
In bootstrap mode, the ROM module will respond only to the bootstrap addresses in
supervisor program space, and provide the information contained in the ROMBS0–
ROMBS3 registers. Bootstrap mode will terminate automatically after the last word of
bootstrap information, ROMBS1 or ROMBS3 is fetched. On the next system clock, the
ROM module will begin responding to control block and array addresses only. If BOOT
= 1, the ROM module will only respond to its control block address and the array base
address specified in ROMBAH and ROMBAL.
The control registers and the array may be accessed via the IMB3 as byte, and aligned
or misaligned word. The ROM array will respond to read operations only. Write oper-
ations will be ignored.
operation in emulation mode.) If ASPC[1] =1, the ROM will only respond to supervisor
mode reads. If ASPC[1] = 0, the ROM will respond to both supervisor and user reads.
If ASPC[0] = 1, the array will respond only to program space accesses. If ASPC[0] =
0, the ROM array will respond to both program and data space accesses.
Access to any address which falls between the last byte of the array and the end of the
address block containing the array (specified by ROMBAH and ROMBAL), will be
ignored, allowing external devices or other modules to adjoin the ROM array in the
address map.
Accesses to the ROM array are only allowed if the STOP control bit in the ROMMCR
register is a 0. If STOP is a 1, ROM array accesses and bootstrap accesses will be
ignored. This allows an external device, or another internal memory module, to
respond to the array address range.
The ROM module allows a byte or aligned word read/write in one IMB3 bus cycle.
Long word read/write or misaligned word read/write will require an additional bus
cycle. Misaligned long word read/write will require a total of 3 bus cycles.
An IMB3 bus cycle requires 2 system clocks minimum. See
CHIP INTEGRATION MODULE 2 (SCIM2E)
accesses.
Freescale Semiconductor, Inc.
For More Information On This Product,
12.6.5 Emulation Mode Operation
Go to: www.freescale.com
MASK ROM MODULE
Rev. 25 June 03
for detailed timing of read/write
describes the read/write
SECTION 4 SINGLE-
MOTOROLA
12-9