MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 400

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.6.6.2 Program Margin Reads
MC68F375
REFERENCE MANUAL
State
S4
S5
The CMFI EEPROM provides a program margin read with electrical margin for the pro-
gram state. Program margin reads provide sufficient margin to assure specified data
retention. The program margin read is enabled when SES = 1 and a programming
write has occurred. To increase the access time of the program margin read, the burst
buffer access time shall be 16 clocks instead of the usual number of clocks as deter-
mined by WAIT[1:0] for the first read access. The program margin read and
subsequent verify reads will return a 1 for any bit that has not completely programmed.
Bits that the programming write left in the non-programmed state will read as a 0. Bits
that have completed programming will read as a 0 and update the data in the program-
ming page buffer so that no further programming of those bits will occur. The program
margin read occurs whenever the burst buffer data is invalid. See section
Read Operation
read must be done for all pages that are being programmed after each program pulse.
This requires two program margin reads for each program buffer. The first required
program margin read should be to an address in either the lower or upper 32 bytes of
the program buffer while the second should be to an address in the other 32 bytes.
High voltage is applied to the array or shadow in-
formation to program the CMFI bit cells.
The pulse width timer is active if SCLKR[2:0]
and HVS can be polled to time the program pulse.
No further programming writes will be accepted.
During programming the CMFI will not generate an
address acknowledge for any array access.
Accesses to the registers are normal register ac-
cesses.
A write to CMFICTL2 can change EHV only.
These reads shall determine if the state of the bits
on the selected page needs further modification by
the program operation.
Once a bit is fully programmed, the data stored in
the program page shall be updated so no further
programming occurs for that bit and the value read
is a 0.
Table 10-13 Program Interlock State Descriptions (Continued)
Program Margin Read Operation:
Program Operation:
for information on when the burst buffer is invalid. A program margin
Freescale Semiconductor, Inc.
Mode
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
0
State
Next
S1
S5
S4
S1
T7
T5
T8
T9
Write EHV = 0, write STOP = 1
or system reset
Transition Requirement
Write SES = 0 or master reset
Write EHV = 1.
Master reset
10.6.5 Array
MOTOROLA
10-30