MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 335

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

CANCTRL2 — Control Register 2
TIMER — Free Running Timer Register
7.8.6 Control Register 2
7.8.7 Free Running Timer
MC68F375
REFERENCE MANUAL
MSB
MSB
15
15
Bit(s)
Bit(s)
0
0
15:8
15:8
RESET:
RESET:
7:0
7:6
5:3
2:0
14
14
0
0
CANCTRL2
PRESDIV
PRESDIV
PSEG1
PSEG2
Name
Name
RJW
13
13
0
0
12
12
PRESDIV
0
0
Prescaler divide factor. PRESDIV determines the ratio between the system clock frequency
and the serial clock (S-clock). The S-clock is determined by the following calculation:
The reset value of PRESDIV is 0x00, which forces the S-clock to default to the same fre-
quency as the system clock. The valid programmed values are 0 through 255.
See
See
Resynchronization jump width. The RJW field defines the maximum number of time quanta
a bit time may be changed during resynchronization. The valid programmed values are 0
through 3.
The resynchronization jump width is calculated as follows:
Resynchronizaton Jump Width = (RJW + 1) Time Quanta
PSEG1[2:0] — Phase buffer segment 1. The PSEG1 field defines the length of phase buffer
segment 1 in the bit time. The valid programmed values are 0 through 7.
The length of phase buffer segment 1 is calculated as follows:
Phase Buffer Segment 1 = (PSEG1 + 1) Time Quanta
PSEG2 — Phase Buffer Segment 2. The PSEG2 field defines the length of phase buffer seg-
ment 2 in the bit time. The valid programmed values are 0 through 7.
The length of phase buffer segment 2 is calculated as follows:
Phase Buffer Segment 2 = (PSEG2 + 1) Time Quanta
Table
Table
Freescale Semiconductor, Inc.
11
11
0
0
Table 7-18 CANCTRL2 Bit Settings
For More Information On This Product,
Table 7-17 PRESDIV Bit Settings
7-18.
7-17.
CAN 2.0B CONTROLLER MODULE
10
10
0
0
Go to: www.freescale.com
9
0
9
0
Rev. 25 June 03
8
0
8
0
TIMER
7
0
7
0
S-clock
RJW
Description
Description
6
0
6
0
=
----------------------------------- -
PRESDIV
5
0
5
0
f sys
PSEG
4
0
4
0
+
1
3
1
3
1
2
0
2
0
0xYF F08A
0xYF F088
MOTOROLA
PSEG2
1
0
1
0
LSB
LSB
7-29
0
0
0
0