MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 39

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

1.3.8 DPTRAM TPU Emulation RAM Module – DPTRAM
1.3.9 1T Flash Electrically Erasable Read Only Memory – CMFI
1.3.10 Static RAM – SRAM
1.3.11 Mask Programmable Read Only Memory – ROM
MC68F375
REFERENCE MANUAL
1.
Note: the MC68F375 contains only a single TPU3. The second TPU3 interface is inactive.
functions replace software functions that would require host CPU interrupt service. Re-
fer to
The RAM module with TPU microcode storage support (DPTRAM) consists of a con-
trol register block and a 6-Kbyte array of static RAM which can be used as a microcode
storage for TPU3 or general purpose memory. Microcode initialization is done by the
host CPU through standard IMB modes of access. Refer to
TPU RAM
The DPTRAM interface includes an IMB3 bus Interface and two
When the RAM is being used in microcode mode, the array may only be accessed by
the TPU3 via a separate local bus, and not via the intermodule bus.
The MC68F375 contains an electrically erasable, programmable 256-Kbyte FLASH
memory (CMFI). The primary function of the CMFI module is to serve as electrically
programmable and erasable non-volatile memory (NVM) to store program instructions
and/or data. It is a non-volatile solid state silicon memory device consisting of an array
of isolated elements, a means for selectively adding and removing charge to the ele-
ments electrically and a means of selectively sensing the stored charge in the
elements. When power is removed from the device, the stored charge of the isolated
elements will be retained. Refer to
(CMFI).
There are two types of SRAM in the MC68F375:
Refer to
The Mask ROM module is designed to be used with the inter-module bus (IMB3) and
consequently any CPU capable of operating on the IMB. A size of 8192 (8K) bytes was
selected to reside on the MC68F375 MCU. The ROM is a “late programmable” type
which means that programming of the array and control register options occurs later
in the processing flow, allowing reduction in cycle time between software code
changes from the user to available devices.
During master reset the ROM will monitor one DATA line (DATA14) to determine if it
should respond as a memory mapped ROM, or be disabled. If the state of DATA14 is
• 8K Static RAM – SRAM. This module is a fast access (2 clocks) general purpose
• 2K (4 x 512 Byte) Patch Static RAM – SRAM. These modules are fast access (2
static RAM (SRAM) for the MCU and is accessed via the IMB.
clocks) general purpose static RAMs (SRAM) for the MCU with a patch option
which provides a method to overlay the internal CMFI memory for emulation.
SECTION 8 TIME PROCESSOR UNIT
SECTION 11 STATIC RANDOM ACCESS MEMORY
(DPTRAM).
Freescale Semiconductor, Inc.
For More Information On This Product,
OVERVIEW DESCRIPTION
Go to: www.freescale.com
Rev. 25 June 03
SECTION 10 CDR MoneT FLASH FOR THE IMB3
3.
SECTION 9 DUAL-PORT
(SRAM).
1
TPU3 interfaces.
MOTOROLA
1-5