MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 229
MC68F375BGMZP33
Manufacturer Part Number
MC68F375BGMZP33
Description
IC MPU 32BIT 33MHZ 217-PBGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68F375BGMZP33.pdf
(616 pages)
Specifications of MC68F375BGMZP33
Processor Type
M683xx 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
217-PBGA
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
256 KB
Data Ram Size
10 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
48
Number Of Timers
16
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
No
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Price
Company:
Part Number:
MC68F375BGMZP33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MC68F375
REFERENCE MANUAL
AMCHAN[1:0]. Address lines to select between the 4 multiplexers. This selection
appears redundant since the final selection between the 4 multiplexers is done by the
QADC64 module. This redundancy is added to reduce the dynamic charging current
required from the input pin. These pins perform a disable function more than a select
function. Only 1 of the 4 multiplexers can be active at a time. These address lines dis-
able the other 3 multiplexers so that none of their switches are closed. As the selected
multiplexer cycles through its various inputs, the other multiplexers draw no dynamic
charging current through their inputs. Without this disable function (as in the external
multiplexer case), pins on all 4 multiplexers would draw current even though only 1
multiplexer would actually be in use.
Assuming that AMCHAN[1:0] change simultaneously with AMMA[2:0], break before
make switching ensures that on each channel change the following occurs:
AMPMUX. When low this signal disables all multiplexer inputs. It is used in conjunction
with AMCHAN[1:0] to reduce dynamic charging current into the AMUX analog pins.
This signal is normally low when the direct inputs to the QADC64 are selected.
AMADB[1:0]. The 2 multiplexer outputs from the AMUX.
1. All 4 multiplexers are disabled
2. The desired input ANX0-15 is selected
3. The appropriate multiplexer is enabled
AMPMUX
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AMCHAN[1:0]
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
XX
00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5-22 AMUX I/O Functionality
AMMA[2:0]
Go to: www.freescale.com
XXX
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
Rev. 25 June 03
AMADB3
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
AMADB2
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
AMADB1
ANX11
ANX13
ANX15
ANX1
ANX3
ANX5
ANX7
ANX9
Z
Z
Z
Z
Z
Z
Z
Z
Z
AMADB0
ANX10
ANX12
ANX14
ANX0
ANX2
ANX4
ANX6
ANX8
Z
Z
Z
Z
Z
Z
Z
Z
Z
MOTOROLA
5-53
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