MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 138

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

RSR — Reset Status Register
4.7.4 Reset Status Register
4.7.5 Reset Timing
MC68F375
REFERENCE MANUAL
MSB
Bit(s)
15
15:8
3:2
7
6
5
4
1
0
Internal byte and aligned word write cycles are guaranteed valid for synchronous
resets. External writes will also complete uncorrupted, provided the data bus is condi-
tioned with a circuit that incorporates RESET, such as that shown in
The reset status register (RSR) contains a bit for each reset source in the MCU. When
a reset occurs, a bit corresponding to the reset type is set. When multiple causes of
reset occur at the same time, more than one bit in RSR may be set. The reset status
register is updated by the reset control logic when RESET is released.
This register can be read at any time; a write has no effect. Bits [15:8] are reserved
and always read zero.
When an external device asserts the RESET pin for at least four clock cycles, the sig-
nal will be latched and held internally until completion of the current bus cycle. Any
further processing of the reset exception is then delayed until the SCIM2E reset control
logic detects that the RESET pin is no longer being externally driven. Two clock cycles
will elapse (during which time the pullup resistor on RESET will pull the pin high) while
the reset control logic switches the RESET pin from an input to an output. RESET will
then be driven low for 512 clock cycles.
If a synchronous internal reset is detected (e.g., from the loss of clock detector or the
test submodule), the reset control logic will wait for bus cycle completion and then
drive RESET low for 512 clock cycles. An asynchronous internal reset (e.g., from the
halt monitor or the software watchdog) will immediately drive RESET low for 512 clock
cycles without waiting for the current bus cycle to complete.
14
Name
POW
EXT
HLT
SYS
TST
SW
—
—
13
Reserved
Power-up reset. Reset caused by the power-up reset circuit.
Software watchdog reset. Reset caused by the software watchdog circuit.
Halt monitor reset. Reset caused by the halt monitor.
Reserved
System reset. Reset caused by a RESET instruction.
Test submodule reset. Reset caused by the test submodule. Used during factory test reserved
operating mode only.
External reset. Reset caused by the RESET pin.
12
Reserved
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
11
For More Information On This Product,
Table 4-23 RSR Bit Descriptions
10
Go to: www.freescale.com
9
Rev. 25 June 03
8
EXT
7
Description
POW
6
SW
5
HLT
4
3
0
Figure
served
Re-
2
0xYF FA06
MOTOROLA
SYS
4-19.
1
LSB
TST
4-56
0