MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 205

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

5.10.5 Periodic/Interval Timer
5.11 Interrupts
MC68F375
REFERENCE MANUAL
The on-chip periodic/interval timer is enabled to generate trigger events at a program-
mable interval, initiating execution of queue 1 and/or 2. The periodic/interval timer
stays reset under the following conditions:
Two other conditions which cause a pulsed reset of the timer are:
During the low power stop mode, the periodic/interval timer is held in reset. Since low
power stop mode causes QACR1 and QACR2 to be reset to zero, a valid periodic or
interval timer mode must be written after stop mode is exited to release the timer from
reset.
When the IMB internal FREEZE line is asserted and a periodic or interval timer mode
is selected, the timer counter is reset after the conversion in progress completes.
When the periodic or interval timer mode has been enabled (the timer is counting), but
a trigger event has not been issued, the freeze mode takes effect immediately, and the
timer is held in reset. When the internal FREEZE line is negated, the timer counter
starts counting from the beginning.
Interrupt recognition and servicing involve interaction between the integration module,
the CPU, and the module requesting interrupt service. This section provides an over-
view of the QADC interrupt process. Polled operation, an alternative to using
interrupts, is discussed along with the different aspects of interrupt operation.
An interrupt is a special form of exception processing. Interrupt requests can be gen-
erated on-chip, or can come from external sources. However, the CPU services all
interrupt requests as though originated by an on-chip module; to the CPU, an external
interrupt request appears to come from the integration module. There are schemes to
prioritize all interrupt requests and to arbitrate between simultaneous requests of the
• Queue 1 and queue 2 are programmed to any queue operating mode which does
• Interval timer single-scan mode is selected, but the single-scan enable bit is set
• IMB system reset or the master reset is asserted
• Stop mode is selected
• Freeze mode is selected
• Roll over of the timer counter
• A queue operating mode change from one periodic/interval timer mode to another
not use the periodic/interval timer
to zero
periodic/interval timer mode, depending on which queues are active in timer
mode.
The periodic/interval timer will not reset for a queue 2 operating mode
change from one periodic/interval timer mode to another periodic/
interval timer mode while queue 1 is in an active periodic/interval
timer mode.
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
NOTE
MOTOROLA
5-29