MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 257

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

CR[0:F] — Command RAM
6.7.3 QSPI Pins
MC68F375
REFERENCE MANUAL
Bit(s)
4:7
0
1
2
3
A maximum of 32 commands can be in the queue. These bytes are assigned an
address from 0x00 to 0x1F. Queue execution by the QSPI proceeds from the address
in NEWQP through the address in ENDQP. (Both of these fields are in SPCR2.)
Refer to
Seven pins are associated with the QSPI. When not needed by the QSPI, they can be
configured for general-purpose I/O.
tions. Register DDRQS determines whether the pins are designated as input or output.
The user must initialize DDRQS for the QSPI to function correctly.
PCS[3:0]
BITSE
CONT
DSCK
Name
DT
6.7.5 Master Mode Operation
NOTES:
CONT
CONT
—
1. The PCS0 bit represents the dual-function PCS0/SS.
7
Continue
0 = Control of chip selects returned to PORTQS after transfer is complete.
1 = Peripheral chip selects remain asserted after transfer is complete.
Bits per transfer enable
0 = Eight bits
1 = Number of bits set in BITS field of SPCR0.
Delay after transfer
0 = Delay after transfer is 17
1 = SPCR1 DTL[7:0] specifies delay after transfer PCS valid to SCK.
PCS to SCK Delay
0 = PCS valid to SCK delay is one-half SCK.
1 = SPCR1 DSCKL[6:0] specifies delay from PCS valid to SCK.
Peripheral chip selects. Use peripheral chip-select bits to select an external device for serial data
transfer. More than one peripheral chip select may be activated at a time, and more than one
peripheral chip can be connected to each PCS pin, provided proper fanout is observed. PCS0
shares a pin with the slave select (SS) signal, which initiates slave mode serial transfer. If SS is
taken low when the QSPI is in master mode, a mode fault occurs.
BITSE
BITSE
Command Control
—
Table 6-19 Command RAM Bit Settings
Freescale Semiconductor, Inc.
6
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
DT
DT
—
5
Go to: www.freescale.com
Rev. 25 June 03
DSCK
DSCK
Table 6-20
—
4
f
SYS
.
for more information on the command RAM.
PCS3
PCS3
—
3
Description
identifies the QSPI pins and their func-
Peripheral Chip Select
PCS2
PCS2
—
2
0xYF FDC0 – 0xYF FDDF
PCS1
PCS1
—
1
PCS0
PCS0
—
0
1
1
MOTOROLA
6-23