MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 330

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
15
14
13
12
11
10
9
8
7
WAKEMSK
SOFTRST
NOTRDY
FRZACK
Name
STOP
SUPV
HALT
FRZ
—
either by the CPU or by the TouCAN, if the SELFWAKE bit is set.
0 = Enable TouCAN clocks
1 = Disable TouCAN clocks
FREEZE assertion response. When FRZ = 1, the TouCAN can enter debug mode when the
IMB3 FREEZE line is asserted or the HALT bit is set. Clearing this bit field causes the Tou-
CAN to exit debug mode. Refer to
0 = TouCAN ignores the IMB3 FREEZE signal and the HALT bit in the module configuration
1 = TouCAN module enabled to enter debug mode.
Reserved
Halt TouCAN S-Clock. Setting the HALT bit has the same effect as assertion of the IMB3
FREEZE signal on the TouCAN without requiring that FREEZE be asserted. This bit is set
to one after reset. It should be cleared after initializing the message buffers and control reg-
isters. TouCAN message buffer receive and transmit functions are inactive until this bit is
cleared.
When HALT is set, write access to certain registers and bits that are normally read-only is
allowed.
0 = The TouCAN operates normally
1 = TouCAN enters debug mode if FRZ = 1
TouCAN not ready. This bit indicates that the TouCAN is either in low-power stop mode or
debug mode. This bit is read-only and is set only when the TouCAN enters low-power stop
mode or debug mode. It is cleared once the TouCAN exits either mode, either by synchroni-
zation to the CAN bus or by the self-wake mechanism.
0 = TouCAN has exited low-power stop mode or debug mode.
1 = TouCAN is in low-power stop mode or debug mode.
Wakeup interrupt mask. The WAKEMSK bit enables wake-up interrupt requests.
0 = Wake up interrupt is disabled.
1 = Wake up interrupt is enabled.
Soft reset. When this bit is asserted, the TouCAN resets its internal state machines
(sequencer, error counters, error flags, and timer) and the host interface registers
(CANMCR, CANICR, CANTCR, IMASK, and IFLAG).
The configuration registers that control the interface with the CAN bus are not changed
(CANCTRL[0:2] and PRESDIV). Message buffers and receive message masks are also not
changed. This allows SOFTRST to be used as a debug feature while the system is running.
Setting SOFTRST also clears the STOP bit in CANMCR.
After setting SOFTRST, allow one complete bus cycle to elapse for the internal TouCAN cir-
cuitry to completely reset before executing another access to CANMCR.
The TouCAN clears this bit once the internal reset cycle is completed.
0 = Soft reset cycle completed
1 = Soft reset cycle initiated
TouCAN disable. When the TouCAN enters debug mode, it sets the FRZACK bit. This bit
should be polled to determine if the TouCAN has entered debug mode. When debug mode
is exited, this bit is negated once the TouCAN prescaler is enabled. This is a read-only bit.
0 = The TouCAN has exited debug mode and the prescaler is enabled.
1 = The TouCAN has entered debug mode, and the prescaler is disabled.
Supervisor/user data space. The SUPV bit places the TouCAN registers in either supervisor
or user data space.
0 = Registers with access controlled by the SUPV bit are accessible in either user or super-
1 = Registers with access controlled by the SUPV bit are restricted to supervisor mode.
Low-power stop mode enable. The STOP bit may only be set by the CPU. It may be cleared
register.
visor privilege mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 7-11 TCNMCR Bit Settings
CAN 2.0B CONTROLLER MODULE
Go to: www.freescale.com
Rev. 25 June 03
7.6.1 Debug Mode
Description
for more information.
MOTOROLA
7-24