MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 416

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

12.3 Programmer’s Model
12.3.1 ROM Control Block
12.3.1.1 ROM Module Control Block Addressing
12.3.2 ROM Array
MC68F375
REFERENCE MANUAL
The ROM module consists of two separately addressable sections. The first is a mem-
ory mapped control register block used for control and configuration information of the
ROM module. The second section is the array itself.
A 32-byte control block contains registers which are used to control ROM module
operation and provide configuration information about the ROM pattern contained in
the module. Configuration information is specified and programmed at the same time
as the contents of the ROM array and on the same mask layer.
The configuration information contained in this block includes array base address
information, bootstrap information and ROM verification information. Control bits are
provided to control array operation. A 19-bit field in the control block section contains
a signature used for identification and verification of the particular ROM pattern con-
tained in the ROM array, see
The control block is restricted to supervisor data space. Unimplemented or reserved
addresses will return 0’s for read accesses. Write accesses to unimplemented or
reserved control block addresses will have no effect. Accesses to unimplemented or
reserved locations will result in bus error (IBERR) being asserted.
The base address of the memory block which the ROM array resides in is specified in
the array base address registers.
The default reset address of the ROM array in the address map of the system is spec-
ified by the customer at ROM programming time. The only restrictions on the base
address is that it must be on a 8-Kbyte boundary and not overlap the module control
register block in the data space memory map. Accesses to unimplemented locations
in the address block will be ignored, allowing another internal module or external
device to respond.
If the base address is set such that the ROM array overlaps the control register block
of the ROM, accesses to the 32 bytes in the array that overlap will be ignored, allowing
the control block to remain accessible.
Note that this is only true with respect to the ROM module. If the control register blocks
of other modules are overlapped by the ROM array, accesses to the overlapped
addresses of other modules will be indeterminate.
• The value of SIGHI and SIGLO which is the ROM signature pattern.
• The default values for the ROM bootstrap information words, ROMBS[0:3]."
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Table
MASK ROM MODULE
Rev. 25 June 03
12-1.
MOTOROLA
12-2