MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 214

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

QACR1 — Control Register 1
5.12.6 QADC64 Control Register 1 (QACR1)
RESET:
MC68F375
REFERENCE MANUAL
Bit(s)
14:13
CIE1
MSB
11:9
15
8:4
2:0
15
12
0
3
Control register 1 is the mode control register for the operation of queue 1. The appli-
cations software defines the queue operating mode for the queue, and may enable a
completion and/or pause interrupt. All of the control register fields are read/write data.
However, the SSE1 bit always reads as zero unless the test mode is enabled. Most of
the bits are typically written once when the software initializes the QADC64, and not
changed afterwards.
PIE1
14
0
Name
MUX
TRG
PSH
PSA
PSL
—
—
SSE1
13
0
Externally multiplexed mode. The MUX bit configures the QADC64 for externally multiplexed
mode, which affects the interpretation of the channel numbers and forces the MA[2:0] pins to be
outputs.
0 = Internally multiplexed, 16 possible channels. AMUX is disabled.
1 = Externally multiplexed, 41 possible channels. This enables the on-chip AMUX.
Reserved
Trigger assignment. TRG allows the software to assign the ETRIG[2:1] pins to queue 1 and
queue 2.
0 = ETRIG1 triggers queue 1; ETRIG2 triggers queue 2
1 = ETRIG1 triggers queue 2; ETRIG2 triggers queue 1
Reserved
Prescaler clock high time. The PSH field selects the QCLK high time in the prescaler. PSH value
plus 1 represents the high time in system clocks
Note that this bit location is maintained for software compatibility with previous versions of the
QADC64. It serves no functional benefit in the MC68F375 and is not operational.
Prescaler clock low time. The PSL field selects the QCLK low time in the prescaler. PSL value
plus 1 represents the low time in system clocks
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
12
0
Freescale Semiconductor, Inc.
11
0
For More Information On This Product,
Table 5-11 QACR0 Bit Settings
MQ1
10
0
Go to: www.freescale.com
9
0
Rev. 25 June 03
8
0
7
0
Description
6
0
5
0
RESERVED
4
0
3
0
2
0
0xYF F40C
MOTOROLA
1
0
5-38
LSB
0
0