MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 201

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MC68F375BGMZP33

Manufacturer Part Number
MC68F375BGMZP33
Description
IC MPU 32BIT 33MHZ 217-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68F375BGMZP33

Processor Type
M683xx 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
217-PBGA
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
256 KB
Data Ram Size
10 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
48
Number Of Timers
16
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68F375BGMZP33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
5.10.4 QADC64 Clock (QCLK) Generation
MC68F375
REFERENCE MANUAL
Figure 5-8
for the A/D converter state machine, which controls the timing of the conversion. The
QCLK is also the input to a 17-stage binary divider which implements the periodic/
interval timer. To retain the specified analog conversion accuracy, the QCLK fre-
quency (F
CHARACTERISTICS.
Before using the QADC64, the software must initialize the prescaler with values that
put the QCLK within the specified range. Though most software applications initialize
the prescaler once and do not change it, write operations to the prescaler fields are
permitted.
QCLK
For software compatibility with earlier versions of QADC64, the defi-
nition of PSL, PSH, and PSA have been maintained. However, the
requirements on minimum time and minimum low time no longer
exist.
A change in the prescaler value while a conversion is in progress is
likely to corrupt the result from any conversion in progress. There-
fore, any prescaler write operation should be done only when both
queues are in the disabled modes.
is a block diagram of the clock subsystem. The QCLK provides the timing
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
) must be within the tolerance specified in
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
CAUTION
NOTE
APPENDIX E ELECTRICAL
MOTOROLA
5-25

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