MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 93

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.3.4 Fast Reference Mode
MC68F375
REFERENCE MANUAL
In fast reference mode, the system clock is generated by the PLL from a reference fre-
quency much higher than that used in slow reference mode (e.g., four MHz). At reset,
the system clock frequency will be equal to twice the reference frequency. This is
accomplished by configuring the W bits to multiply by four, and setting the X bit to
divide by two for a net result of multiplying by two. The frequency may be multiplied
using the W bits or divided using the X and Y bits to generate the desired system clock
frequency. This mode improves stability over the slow reference mode and, like slow
reference mode, provides a 50% duty cycle system clock regardless of the reference
duty cycle.
The W bits are in the feedback path of the VCO. They can be programmed to multiply
the reference frequency by a factor from one to eight. These bits come out of reset as
0b11, so that the system clock frequency is four times the reference clock frequency.
After reset, the W bits can be changed to multiply the reference to the desired system
clock frequency. Changing of the W bits will result in PLL unlocking for the PLL lock
time specified.
The X bit on the VCO output is used to divide the VCO frequency by two or one. This
bit comes out of reset clear (divide by two) so that the system clock frequency is actu-
ally one half of what it is multiplied to by the W bits. This bit may be set to increase the
system frequency to twice that of the frequency when this bit is clear.
The Y bit divider is a six-stage divider chain in the clock output path, whose output tap
is controlled by the three Y register bits. It can divide the output of the VCO down by
powers of two to as much as 64, providing a large number of programmable frequen-
cies in this mode.
Table 4-7
using a 4.0-MHz reference. The frequency representing the reset configuration is
shaded in this table. This frequency ends up being twice the reference frequency when
the X bit is cleared, or 8.0 MHz with a 4.0-MHz reference clock. The X bit can then be
set to select a system frequency of four times the reference frequency, or 16.0 MHz
with a 4.0-MHz reference clock with no PLL re-lock time requirements. Combinations
of programmed values for the W, X, and Y bits which would exceed maximum system
or VCO core frequencies are not supported and are left blank, as a reminder, in the
table for frequencies above 33 MHz.
Setting Y to 7 in this mode has the same effect as setting it to 6; the
maximum divisor is 2
reduces the system clock frequency thereby conserving power.
Since the X and Y bits are not in the PLL feedback path, the PLL will
not have to relock to the new target frequency when they are
changed. The Y bits are cleared to all zeros at reset.
block diagram of the fast reference mode architecture.
gives example values of the system clock frequency in fast reference mode
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
6
. Dividing the PLL output clock with the Y bits
Rev. 25 June 03
NOTE
Figure 4-3
MOTOROLA
is a
4-11