MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 405

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.6.7.2 Erase Margin Reads
10.6.7.3 Erasing Shadow Information Words
10.6.8 Stop Operation
10.6.8.1 Low Power Stop Clock Operation
10.6.8.2 STOP Recovery
MC68F375
REFERENCE MANUAL
The CMFI EEPROM provides an erase margin read with electrical margin for the erase
state. Erase margin reads provide sufficient margin to assure specified data retention.
The erase margin read is enabled when SES = 1 and the erase write has occurred.
The erase margin read and subsequent on page erase verify reads will return a 0 for
any bit that has not completely erased. Bits that have completed erasing will read as
a 1. To increase the access time of the erase margin read the access time shall be 16
clocks instead of the usual number of clocks as determined by WAIT[1:0] for the first
read access. The erase margin read occurs while doing the transfer from the array to
the burst buffer. All locations within the block(s) that are being erased must read as a
1 to determine that no more erase pulses are required.
The shadow information words are erased with either CMFI array block 0 or block 2
depending upon the array configuration. To verify that the shadow information words
are erased the SIE bit in CMFIMCR should be set to 1 during the erase margin read
while the shadow information is read. For the erase operation to be completed block
0 or 2 must also be fully verified.
Setting SIE = 1 will disable normal array access and should be cleared after verifying
the shadow information.
The CMFI EEPROM goes into a low power operation, or stop operation, while STOP
= 1. Setting STOP to 1 will clear EHV to a 0. When the STOP bit is set only the control
registers can be accessed on the CMFI EEPROM. The CMFI EEPROM array may not
be programmed, erased or read while STOP = 1. With STOP = 1 and LOCK = 1 the
array may be mapped to another location in the memory map, and the array Address
Space may be changed. During stop operation the CMFI may enter low power stop
clock operation.
The low power stop clock operation is the lowest power configuration of the CMFI
EEPROM, disabling the internal clock. This operation is entered when STOP = 1 and
the correct system clock disable (ICLKDIS[N]) is asserted and HVS = 0. The BIU will
disable the system clock to the state machine at the completion of required functions
to protect the CMFI EEPROM after the STOP bit is set and ICLKDIS[N] is asserted.
Once the CMFI EEPROM is in low power stop clock operation, all accesses by the
IMB3 will be ignored, and AACKB will not be asserted until ICLKDIS[N] is cleared by
the IM. When ICLKDIS[N] is cleared, the internal clocks will be enabled and the CMFI
EEPROM register control block will respond to IMB3 accesses.
The CMFI requires 16 clocks after writing STOP = 0 prior to a normal CMFI EEPROM
array read. The access time of the first CMFI array read shall be 16 clocks instead of
the usual number of clocks as determined by WAIT[1:0]. To meet this requirement the
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
10-35